DMA Controller Channel Grouping for Multiprocessor Load Reduction
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Solution Overview
Problem
Existing direct memory access (DMA) schemes in multiprocessing systems require multiple sub-processors to generate numerous DMA commands, increasing processor load and reducing processing capability, especially in graphic applications that demand high data processing rates, and face inefficiencies in data transmission between memories connected to independent buses.
Innovation Solution
A direct memory access controller (DMAC) that classifies DMA channels into groups, allowing external processors to control them through a crossbar switch and register banks, enabling efficient data transmission by setting sub-channel registers for large data transfers, reducing processor control load and enabling sub-channels automatically for data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple sub-processors are used to generate DMA commands for high data processing rates, then data processing capability is improved, but processor load increases and processing capability is reduced
Solution Approach 1:
The patent segments DMA channels into multiple groups (first DMA channel group and second DMA channel group), with each group independently controllable. This segmentation allows the system to activate only the necessary channel groups for current operations, reducing the overall processor load while maintaining high data processing rates when needed.
Solution Approach 2:
The patent implements dynamic control of DMA channel groups through enable/disable functionality. The processor can dynamically enable or disable specific DMA channel groups based on real-time data transmission requirements, allowing the system to adapt processor load to actual needs rather than maintaining constant high-level operation.
2Measurement precision
If DMA channels are controlled individually for precise data transmission, then transmission accuracy is improved, but control complexity increases
Solution Approach 1:
The patent merges multiple DMA channels into controllable groups. By grouping channels together, the system reduces control complexity as the processor can enable or disable entire groups with single operations rather than managing each channel individually, while still maintaining the ability to control specific channels when precise control is required.
3Speed
If all DMA channels are enabled for rapid data transmission, then data transmission speed is improved, but system resource consumption increases
Solution Approach 1:
The patent implements dynamic enablement of DMA channel groups based on actual transmission needs. The processor can enable specific channel groups only when data transmission is required and disable them when not needed, allowing the system to achieve high transmission speeds when necessary while conserving system resources during normal operation.
Data Source
AI summary
Provided is a direct memory access (DMA) controller. The DMA controller includes a plurality of channel groups and a channel group controller. Each of the channel groups has a plurality of DMA channels, and the channel group controller controls enablement of the DMA channels in units of channel groups. Herein, the channel group controller enables the DMA channels of at least one of the channel groups in data transmission.