DMA Controller Programming via Hardware Contiguity Checking
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Solution Overview
Problem
Existing systems struggle to manage discontinuities in physical memory space when programming a DMA controller directly by a user program, as they lack access to physical addresses, leading to reduced addressable memory space and inability to implement conventional discontinuity management techniques.
Innovation Solution
A method and system that utilize a memory management unit and a hardware contiguity checking module to translate virtual addresses into physical addresses, identify sub-blocks without discontinuities, and deliver programming elements to the DMA controller, allowing user programs to manage physical memory space discontinuities without OS intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If user programs directly program the DMA controller with virtual addresses, then OS intervention is eliminated and processing speed improves, but the system cannot manage physical memory discontinuities and addressable memory space is reduced
Solution Approach 1:
A contiguity checking module is introduced as an intermediary component between the user program and the DMA controller. This module automatically checks virtual addresses for contiguity and manages the translation to physical addresses, allowing user programs to work with virtual addresses while ensuring proper handling of memory discontinuities. The intermediary handles the complexity of address management without requiring OS intervention, thus maintaining both speed and addressable memory space.
Solution Approach 2:
The contiguity checking module provides self-service functionality by automatically detecting and managing memory contiguity issues without external intervention. When a user program issues a DMA transfer request with virtual addresses, the module autonomously verifies contiguity, identifies discontinuities, and adjusts the transfer parameters accordingly, eliminating the need for OS involvement while maintaining proper memory management.
2Reliability
If the OS translates virtual addresses to physical addresses for DMA programming, then memory security is maintained, but processing speed decreases due to OS intervention
Solution Approach 1:
The address translation and contiguity checking functionality is extracted from the operating system and implemented as a dedicated hardware module. This extraction allows the critical path of DMA programming to bypass the OS, eliminating the speed penalty of context switches and system calls, while the hardware module continues to enforce memory security rules and manage address translations autonomously.
Solution Approach 2:
The software-based address translation and contiguity management performed by the OS is replaced with a hardware-based contiguity checking module. This mechanical substitution enables the system to perform address validation and translation operations in hardware, significantly reducing processing time while maintaining the same security and management capabilities.
3Ease of operation
If implicit addressing is used to program DMA controller, then user mode programming is enabled, but addressable memory space is reduced by half
Solution Approach 1:
The system changes the addressing parameter from implicit physical addressing to explicit virtual addressing with contiguity checking. Instead of using implicit physical addresses that limit the addressable space, the system allows user programs to specify virtual addresses and enables the contiguity checking module to validate and manage the actual physical address mapping, thereby expanding the addressable memory space while maintaining user-mode programming capability.
Data Source
AI summary
A method is provided for programming a DMA controller in a system on a chip. According to the method, a memory management unit translates a programming virtual address into a programming physical address according to a translation table. A first sub-block without discontinuity beginning at the programming physical address and ending at an end address equal to the physical address immediately preceding a first discontinuity is formed, with the first discontinuity being determined by a discontinuity module according to information supplied by a memory management unit. Some of the programming elements intended for the DMA controller are defined according to the first identified sub-block. Also provided is a system on a chip.