DMA Controller Dual Register Transfer Configuration
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Solution Overview
Problem
Conventional DMA transfer methods overload the CPU by requiring it to wait for current data transfers to complete before configuring settings for next transfers, leading to inefficient processing and potential overwriting of settings.
Innovation Solution
A DMA controller with first and second transfer setting registers and flags to control writing, allowing next transfer settings to be stored and configured during ongoing transfers, preventing overwriting and improving efficiency by using flags to manage write enable/disable states and a comparator for standard transfer count notifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU waits for current DMA transfer to complete before configuring next transfer settings, then the settings are not overwritten, but the CPU becomes overloaded and processing speed decreases
Solution Approach 1:
The patent applies preliminary action by allowing the CPU to configure next DMA transfer settings in advance during ongoing transfers. The second transfer setting register enables preconfiguration of subsequent transfer parameters (source address, destination address, transfer count) without waiting for current transfer completion, thus improving processing speed while maintaining setting integrity through the flag mechanism
Solution Approach 2:
The patent uses an intermediary mechanism (the flag and comparator system) to mediate between the CPU's configuration requests and the DMA controller's transfer execution. The flag acts as an intermediary indicator that tells the CPU when it is safe to write settings, while the comparator monitors transfer completion and automatically manages the flag state, preventing overwriting without requiring CPU to wait
2Productivity
If the CPU configures next DMA transfer settings during ongoing transfers, then processing speed improves, but the settings may be overwritten before execution
Solution Approach 1:
The patent implements feedback through the comparator that continuously monitors the transfer count and provides feedback about transfer completion status. When the transfer count reaches zero, the comparator generates an interruption signal that triggers the flag to be set, providing feedback to the CPU that the DMA transfer is complete and it is safe to write new settings to the second register, thus preventing overwriting while maintaining high processing speed
Solution Approach 2:
The patent applies preliminary anti-action by using the flag to preemptively prevent the CPU from writing to the second transfer setting register when a DMA transfer is ongoing. The flag is set in advance based on the comparator's monitoring, creating a protective barrier that stops potential overwriting before it can occur, while still allowing configuration during transfers when the flag is clear
Data Source
AI summary
DMAC includes current transfer setting registers and next transfer setting registers. Each of the current transfer setting registers stores transfer source address, transfer destination address and transfer count. The next transfer setting registers stores a transfer setting of a DMA transfer carried out after completing a DMA transfer according to a current transfer setting stored in the current transfer setting registers as a next transfer setting. Further, flags are provided for controlling to write to each of the next transfer setting registers.