DMA Controller for Embedded Processor Data Communication
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Solution Overview
Problem
Conventional methods for data communication between an embedded processor and dedicated functional units in SoC designs burden the processor with extensive data processing, leading to reduced efficiency and inability to meet practical application requirements, especially when dealing with large data amounts.
Innovation Solution
The method involves dividing internal memory into multiple on-chip storage units with independent read/write operations, configuring a memory interface controller and a DMA controller with request allocation units, and utilizing a dedicated functional module to manage data transfer through the DMA controller, reducing processor burden and enhancing data processing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor directly performs read and write operations for data communication with dedicated functional units, then data communication can be completed, but the processor burden increases greatly and processing efficiency decreases
Solution Approach 1:
The patent introduces a DMA controller as an intermediary device between the processor and dedicated functional units. The DMA controller handles data transfer operations independently, allowing the processor to focus on high-level processing while the DMA controller manages the actual data movement between memory and functional units, thus resolving the contradiction between maintaining communication capability and preserving processor efficiency
Solution Approach 2:
The patent extracts the data transfer functionality from the processor and assigns it to a separate DMA controller. This extraction allows the processor to offload routine data communication tasks, reducing its burden and preventing it from being bottlenecked by large volumes of data transfer operations while maintaining full data communication capability
2Productivity
If a DMA controller is added to handle data transfer operations, then processor burden is reduced, but system complexity increases due to additional components and bus sharing
Solution Approach 1:
The DMA controller is designed with multi-functionality to handle various data transfer operations (read, write, interrupt management) and can serve multiple dedicated functional units. This universal design reduces the need for separate dedicated controllers for each function, thereby reducing overall system complexity while maintaining high processor efficiency
Solution Approach 2:
The DMA controller is designed to operate autonomously, managing its own data transfer operations, buffer management, and interrupt generation without requiring constant processor intervention. This self-service capability reduces the need for complex control logic and processor-DMA coordination, simplifying the system architecture while preserving processor efficiency
3Extent of automation
If the DMA controller shares the system bus with the processor, then data transfer can be performed independently, but the data transmission bandwidth is occupied and overall processing efficiency decreases
Solution Approach 1:
The patent segments the data transfer operations into separate channels or time slots, allowing the DMA controller and processor to share the system bus without constant conflict. By dividing the bus access into organized segments or using dedicated transfer windows, the system maintains autonomous data transfer capability while minimizing bandwidth contention and preserving overall processing efficiency
Data Source
AI summary
A method and an apparatus for an embedded processor to perform fast data communication, and a storage medium are provided. The method comprises: dividing an internal memory into multiple on-chip storage units sequentially assigned with consecutive addresses; configuring a memory interface controller connected to the internal memory, the memory interface controller comprising multiple memory interface control units; configuring an on-chip processor and a DMA controller respectively connected to the memory interface controller, the DMA controller comprising multiple request allocation units in one-to-one correspondence with the memory interface control units; configuring a dedicated functional module connected to the DMA controller, and in a case where the on-chip processor and the DMA controller perform a read and/or write request, the memory interface control unit matches a corresponding on-chip storage unit, so as to read and/or write data in the internal memory, and returns the read data to an original request module.