DMA Controller Firmware Synchronization for Multi-Source Data Sequencing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing direct memory access (DMA) controllers face challenges in synchronizing data from multiple unsynchronized sources, leading to issues with data order and interlaced data transmission, which limits their ability to manage complex data sequences without central processing unit intervention.
Innovation Solution
A DMA controller with a read management module and firmware that associates read pointers with each buffer memory, synchronizing firmware execution to determine the data order and using circular buffer memories with write and read pointers to manage data flow, allowing for deterministic data sequencing and synchronization without relying on central processing unit synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple buffer memories are used to store data from different sources, then data can be transferred without central processing unit intervention, but the data order and synchronization between sources cannot be accurately maintained
Solution Approach 1:
The system segments the data transfer management by associating a dedicated firmware with each buffer memory. Each firmware independently manages its associated buffer, reading data and updating read pointers. This segmentation allows parallel operation of multiple buffers while maintaining individual control over data order within each buffer.
Solution Approach 2:
The invention implements feedback mechanisms through read pointers that track the position of data within each buffer memory. The firmwares continuously monitor and update these pointers based on data consumption, providing feedback that enables accurate tracking of data order and synchronization status across multiple sources without central processing unit intervention.
2Reliability
If an ordered list of buffer memories is managed by the DMA controller, then data can be transmitted in a predetermined order, but the complexity of the controller increases and accurate synchronization of multiple sources is still limited
Solution Approach 1:
Each buffer memory is equipped with its own firmware that autonomously manages data reading and read pointer updates. This self-service approach eliminates the need for the DMA controller to manually manage the ordered list of buffers, significantly reducing controller complexity while maintaining predetermined data order through the coordinated execution of multiple firmwares.
Solution Approach 2:
The firmwares are pre-configured with the necessary logic to read data in the correct order from their associated buffers and update read pointers accordingly. This preliminary action ensures that data is transmitted in the predetermined order without requiring complex real-time management by the DMA controller.
3Device complexity
If buffer memories are used without associated firmwares, then the controller structure is simpler, but the ability to synchronize data reading and update pointers accurately is reduced
Solution Approach 1:
The invention merges the firmware functionality directly with each buffer memory, creating an integrated unit where the firmware and buffer work together as a single entity. This merging maintains a relatively simple overall controller structure while achieving high synchronization accuracy through the tight coupling of data storage and management logic at each buffer level.
Data Source
AI summary
A direct memory access controller including: a transfer module that transfers data from several data sources to at least one addressee for these data, through several buffer memories each including a predetermined number of successive elementary memory locations; a read management module that reads data stored in the buffer memories and that transfers them in sequence to the addressee; and a storage module that stores read pointers associated respectively with each buffer memory, each read pointer indicating an elementary location of the buffer memory with which it is associated and in which data can be read, wherein the buffer memories are associated respectively with each data source, and for each buffer memory, the controller includes means for executing a firmware that reads data and updates a read pointer associated with this buffer memory, and for synchronising execution of the firmwares as a function of a predetermined order of data originating from buffer memories required in a data sequence to be transferred to the addressee.