Programmable DMA Controller for Non-Sequential Peripheral Configuration
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Solution Overview
Problem
Existing direct memory access (DMA) controllers are inefficient in reconfiguring core independent peripherals (CIPs) due to scattered configuration registers and the need for cross-connected DMA peripherals, leading to slow writing speeds and potential errors.
Innovation Solution
A programmable arbitrary sequence DMA controller with a first and second address pointer register, data latch, address latch, multiplexer, and control logic that allows for external triggering and indirect memory addressing, enabling non-sequential memory transfers without the need for cross-connected DMA controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two DMA peripherals are used with cross-connection to reconfigure CIPs, then the reconfiguration capability is achieved, but the device complexity increases and writing speed decreases
Solution Approach 1:
The patent segments the DMA controller into two independent address pointer registers (first and second) that can independently access different memory locations. This allows arbitrary sequence access to scattered CIP configuration registers without requiring cross-connected DMA peripherals, thereby achieving reconfiguration capability while reducing device complexity
Solution Approach 2:
The patent creates a universal DMA controller that can handle both sequential and non-sequential memory access patterns through its dual address pointer architecture. The controller can configure multiple CIPs with scattered registers across different SFR address banks using a single unified structure, eliminating the need for specialized cross-connected DMA pairs
2Adaptability or versatility
If two DMA peripherals are cross-connected for CIP reconfiguration, then arbitrary sequence access is enabled, but the reliability decreases due to error propagation
Solution Approach 1:
The patent segments the addressing function into two independent address pointer registers that operate autonomously. The first address pointer register accesses source memory locations while the second accesses destination locations, eliminating the error propagation risk inherent in cross-connected DMA systems where a fault in one peripheral affects the other
Solution Approach 2:
The patent introduces an intermediary data latch that buffers data between the two independent DMA address pointers. This intermediary structure decouples the two access operations, allowing arbitrary sequence access to scattered CIP registers while preventing error propagation between the source and destination addressing operations
3Adaptability or versatility
If program firmware is used to reconfigure CIPs, then flexibility is achieved, but the response time increases due to latency
Solution Approach 1:
The patent implements a self-service DMA controller that can autonomously perform arbitrary sequence memory transfers without CPU intervention. The dual address pointer registers independently manage source and destination addressing, enabling the controller to reconfigure CIPs directly from memory without requiring slow firmware execution, thereby reducing response time while maintaining flexibility
Solution Approach 2:
The patent prepares configuration data in advance in memory at specific addresses. When reconfiguration is needed, the DMA controller directly transfers this pre-prepared data to the CIP registers using its dual address pointer mechanism, eliminating the need for real-time firmware processing and significantly reducing response time
Data Source
AI summary
A programmable arbitrary sequence direct memory access (DMA) controller accesses sequentially addressed memory locations (source or destination) using address pointer registers. Each sequentially addressed memory location containing an indirect memory address is stored in an address latch and used to access the actual non-sequential memory location to be accessed by the DMA transfer.