DMA Controller Non-Sequential Data Transfer
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Solution Overview
Problem
Existing DMA systems require requestors to reorder data received from memory, which increases complexity and resource consumption, as data is typically transferred in a manner optimized for the memory architecture rather than the requestor's needs.
Innovation Solution
A DMA controller that interfaces between the memory and requestor, capable of reordering data from a row-oriented arrangement to a column-oriented arrangement, allowing the memory to provide data in the requested order directly to the requestor, thereby eliminating the need for reordering by the requestor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred in a manner optimized for memory architecture (consecutive addresses), then memory bandwidth utilization is improved, but requestor-side reordering complexity increases
Solution Approach 1:
The patent introduces a DMA controller as an intermediary device between the memory and the requestor. The DMA controller receives data from memory in consecutive address order (optimized for memory bandwidth) and automatically reorders it according to the requestor's needs, eliminating the need for the requestor to perform complex reordering operations. This mediator handles the reordering complexity internally while presenting a simplified interface to the requestor.
Solution Approach 2:
The DMA controller performs self-service by automatically managing the reordering of data without requiring external intervention from the requestor. The controller monitors its own buffer contents and autonomously determines when data is ready to be transferred to the requestor in the correct order, reducing the computational burden on the requestor system.
2Speed
If data is transferred in a manner optimized for memory architecture, then memory access efficiency is improved, but requestor processing time increases
Solution Approach 1:
The DMA controller performs preliminary actions by pre-fetching data from memory in consecutive address order (which is efficient for memory access) and storing it in its internal buffer before the requestor needs it. The controller also pre-processes the reordering of this data, so that when the requestor requests the data, it is already prepared in the correct sequence, eliminating processing delays for the requestor.
Solution Approach 2:
The DMA controller maintains continuous useful action by keeping its buffer populated with pre-fetched data and continuously monitoring for transfer opportunities. This ensures that data flows continuously from memory through the DMA controller to the requestor without idle periods, maximizing memory access efficiency while ensuring the requestor receives data ready for immediate processing.
3Adaptability or versatility
If data is reordered by the requestor, then data arrangement flexibility is improved, but system resource consumption increases
Solution Approach 1:
The DMA controller serves as an intermediary that handles the computationally intensive reordering operations, freeing the requestor from this burden. The controller maintains flexibility in data arrangement by allowing the requestor to specify desired data sequences, while the DMA controller's internal buffer and control logic handle the actual reordering, reducing the energy consumption of the overall system.
Solution Approach 2:
The patent replaces the mechanical/computational reordering operations that would otherwise be performed by the requestor's processor with a dedicated DMA controller's specialized hardware logic. This substitution moves the reordering function from general-purpose processing (higher energy consumption) to specialized hardware (lower energy consumption), maintaining data arrangement flexibility while reducing system resource usage.
Data Source
AI summary
In one example, a direct memory access controller includes a memory interface, a requestor interface, and an address generator. The memory interface is configured to cause a memory to provide at least a subset of data stored in the memory. The requestor interface is configured to receive a request for a consecutively addressed subset of the data stored in the memory to be provided in a non-consecutive order. The address generator is in communication with the requestor interface and the memory interface. The address generator is configured to, based on the request, sequentially generate non-consecutive addresses of the requested subset of the data to cause the memory to provide the requested subset of data in the requested non-consecutive order.