DMA Controller Packet Offloading to NIC Co-processor
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Solution Overview
Problem
Traditional network controllers lack mechanisms to offload specialized operations such as encryption and decryption to a co-processor without involving the host processor, limiting their ability to handle secure and high-speed data processing tasks efficiently.
Innovation Solution
A Direct Memory Access (DMA) controller within a host device is used to detect DMA descriptors and move packets to either host main memory, NIC memory, or co-processor memory, utilizing a ternary content-addressable memory (TCAM) method for data movement and defining new hardware descriptor formats to enable special purpose operations like encryption and decryption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional hardware queues (WQ, RQ, CQ) are used for packet transmission and reception, then network packet transmission and reception can be performed without host processor involvement, but specialized operations such as encryption or decryption cannot be completed without host processor involvement
Solution Approach 1:
The patent segments the network controller functionality by introducing a co-processor that handles specialized operations (encryption, decryption, compression) separately from the main hardware queues. This allows the traditional WQ/RQ/CQ model to continue handling standard packet operations while the co-processor handles specialized operations independently, resolving the contradiction between maintaining high-speed packet processing and adding specialized operation capabilities.
Solution Approach 2:
The patent introduces a co-processor as an intermediary between the host processor and the network interface. This co-processor acts as a mediator that can perform specialized operations on packets without requiring host processor involvement, thus enabling versatile operations while maintaining the efficiency of hardware-based packet processing. The co-processor receives descriptors from the host and processes packets independently.
2Reliability
If host processor is involved in specialized operations like encryption and decryption, then secure data processing can be performed, but host processor cycles are consumed reducing overall processing efficiency
Solution Approach 1:
The patent extracts the specialized operation functionality from the host processor and places it in a dedicated co-processor. This extraction allows secure operations (encryption, decryption) to be performed independently without consuming host processor cycles. The co-processor has its own descriptor queues and can operate autonomously, thus maintaining security capabilities while preserving host processor efficiency for other tasks.
3Adaptability or versatility
If more data movement operations are performed between host device and memory for security features, then security processing capability increases, but the complexity of data movement management increases
Solution Approach 1:
The patent creates a universal descriptor format that can handle both traditional packet operations and specialized security operations through a single unified interface. The DMA controller and co-processor use the same descriptor structure (with additional fields for security operations), eliminating the need for separate complex data movement management paths. This universal approach allows security features to be added without proportionally increasing management complexity.
Data Source
AI summary
In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.