DMA Controller Single Bus Command Direct Data Transfer
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Solution Overview
Problem
Current processing systems require a two-step process for data transfer between memory devices, involving a processor, which is inefficient and unnecessary, as data often needs to be transferred directly between devices without processor intervention.
Innovation Solution
A bus mastering device sends a single bus command with DMA circuitry to directly transfer data between two address locations on a two-channel bus, allowing for simultaneous read and write operations or coordinated data transfer between slave devices without processor mediation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a two-step process is used for data transfer between memory devices through the processor, then data can be transferred between devices, but the transfer efficiency is reduced and processor involvement increases
Solution Approach 1:
The patent extracts the data transfer function from the processor by introducing a DMA controller that can independently perform data transfers between memory devices. The DMA controller is separated from the processor, allowing it to handle data transfer operations without processor intervention, thus improving transfer efficiency and reducing processor involvement time.
Solution Approach 2:
The DMA controller acts as an intermediary between the processor and memory devices for data transfer operations. Instead of the processor directly managing data transfers, the DMA controller mediates these transfers by autonomously reading from source memory addresses and writing to destination memory addresses, thereby eliminating the need for processor involvement in each transfer step.
2Ease of operation
If separate read and write channels are used in standardized bus architecture, then independent access to memory is enabled, but direct data transfer between devices without processor mediation is not achieved
Solution Approach 1:
The patent merges the read and write operations into a single coordinated data transfer process handled by the DMA controller. The DMA controller simultaneously reads from a source memory address and writes to a destination memory address in response to a single bus command, combining what would traditionally be separate operations into one unified transfer action, thereby simplifying the overall data transfer process.
Solution Approach 2:
The DMA controller serves multiple functions: it acts as a bus master to initiate transfers, manages both read and write operations, coordinates data movement between different memory devices, and handles address decoding. This multi-functionality consolidates what would traditionally require separate dedicated circuits, enabling direct data transfer while maintaining ease of operation.
3Speed
If a single bus command is used to transfer data directly between devices, then transfer speed increases, but the bus interconnect structure becomes more complex
Solution Approach 1:
The DMA controller is designed to self-manage the data transfer process without requiring complex external control structures. It autonomously decodes bus commands, determines source and destination addresses, manages read/write operations, and coordinates the actual data movement. This self-service capability allows high-speed direct transfers while keeping the overall bus interconnect structure relatively simple, as the DMA controller handles the complexity internally.
Data Source
AI summary
A processing system and method for transferring data in a processing system. The processing system includes a bus mastering device, a plurality of slave devices, and a bus interconnect configured to switch the bus mastering device between the slave devices. Each of the slave devices has a plurality of addresses. The bus interconnect includes a DMA controller configured to transfer data from a first one of the addresses to a second one of the addresses in response to a single bus command from the bus mastering device.