DMA Controller User Mode Programming via Dedicated Address Translation
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Solution Overview
Problem
Conventional methods for programming a DMA controller in user mode reduce the addressable memory space by half due to the requirement of setting the most significant bit to 1 for implicit addressing, which is detrimental for systems with memory areas or peripheral devices starting with 1.
Innovation Solution
A method and system that utilize a dedicated instruction to translate virtual addresses into physical addresses and apply signals to select and store physical addresses in DMA controller registers, without altering the existing CPU, MMU, or memory management protocols, ensuring secure access and full memory utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If implicit addressing with most significant bit set to 1 is used for programming DMA controller, then user mode programming is enabled, but addressable memory space is reduced by half
Solution Approach 1:
The patent introduces a dedicated instruction as an intermediary mechanism between the user program and the DMA controller registers. This instruction enables user mode programming by acting as a mediator that translates user-level virtual addresses into the required physical address format for DMA registers, without requiring user programs to directly manipulate the most significant bit or access physical addresses. The dedicated instruction handles the address translation and register selection internally, resolving the contradiction between enabling user mode operation and preserving full addressable memory space.
2Area of stationary object
If dedicated instruction with virtual address translation is used, then full memory space is utilized, but system complexity increases
Solution Approach 1:
The dedicated instruction is designed to perform multiple functions within a single operation: it translates virtual addresses to physical addresses, selects the appropriate DMA register (source, destination, or size), and initiates the store operation atomically. This multi-functionality reduces the need for multiple separate instructions and complex programming sequences, thereby limiting the increase in system complexity while achieving full memory space utilization.
3Reliability
If virtual address translation is performed for DMA registers, then security is maintained, but programming time increases
Solution Approach 1:
The dedicated instruction performs virtual address translation in advance as part of the register programming operation itself, rather than requiring separate translation steps. The MMU translates the virtual address to a physical address before the store operation is executed, and this translation is integrated into the atomic instruction sequence. This preliminary action ensures security requirements are met while minimizing the time penalty, as the translation occurs concurrently with the register programming rather than sequentially.
Data Source
AI summary
A procedure is provided for programming a DMA controller of a system on a chip that includes a CPU, an MMU, a DMA controller including source, destination, and size registers, and entities that are each identified by a physical address and addressable by applying that physical address to the address bus. In response to a first dedicated instruction of a user program, the virtual address is translated into a corresponding physical address, the corresponding physical address is applied to the address bus, a signal having a first value is delivered to the DMA controller, and a signal having a second value is delivered to the entities. When the signal delivered to the DMA controller has the first value, the source register or the destination register of the DMA controller is selected and the corresponding physical address on the address bus is stored in the selected register.