DMA Controller Zigzag Buffering for Backward Data Access
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Solution Overview
Problem
Existing memory access methods are inefficient, particularly when accessing data stored in memory, as they require significant CPU resources and do not allow for efficient backward data retrieval, leading to increased system load during multi-processing operations.
Innovation Solution
A memory access apparatus and method utilizing a DMA controller that enables backward data access by buffering data in a zigzag pattern, allowing the DMA controller to read data in one direction and write it in another, with a processing module reading the data in the opposite direction, thereby reducing CPU resource usage and enabling efficient backward data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DMA controller accesses data in forward direction only, then data transfer efficiency is improved, but backward data access capability deteriorates
Solution Approach 1:
The patent applies inversion by enabling the DMA controller to access data in both forward and backward directions. The controller alternates between forward and backward access modes based on search requirements, allowing the search engine to efficiently search data in either direction without being constrained to a single access pattern.
Solution Approach 2:
The patent implements dynamic data buffering by maintaining multiple buffers (first buffer and second buffer) that can be dynamically switched between forward and backward access operations. The system dynamically allocates and switches buffers based on whether forward or backward search is required, enabling flexible adaptation to different search scenarios.
2Ease of operation
If CPU directly accesses memory data, then data access control is simplified, but system load increases
Solution Approach 1:
The patent extracts the data transfer function from the CPU by implementing a dedicated DMA controller that handles all memory-to-search-engine data transfers. This extraction allows the CPU to focus on control functions while the DMA controller manages the actual data movement, reducing system load during multi-processing operations.
Solution Approach 2:
The patent introduces the DMA controller as an intermediary between the CPU and memory system. The CPU issues search commands to the DMA controller, which then autonomously manages data buffering, directional access, and transfer operations, reducing CPU resource consumption while maintaining control simplicity.
3Device complexity
If single buffer is used for data buffering, then device complexity is reduced, but backward search capability deteriorates
Solution Approach 1:
The patent merges forward and backward search capabilities into a unified buffer management system. By using a single buffer structure that supports bidirectional access and dynamic switching, the system combines the simplicity of single-buffer design with the functionality of multi-buffer systems, achieving both low complexity and full backward search capability.
Solution Approach 2:
The patent adds the dimension of access directionality to the buffer structure. Instead of using multiple separate buffers for forward and backward access, the system uses a single buffer that can be dynamically configured for either access direction, effectively adding a temporal/directional dimension to the buffer's functionality without increasing structural complexity.
Data Source
AI summary
Disclosed are a direct memory access (DMA) apparatus and method. The DMA apparatus may include memory, a buffer, a DMA controller suitable for setting group regions from which data of the memory is to be read, reading data of each odd-numbered group region in a first direction and writing the read data of each odd-numbered group region in the buffer in the first direction, and reading data of each even-numbered group region in the first direction and writing the read data of each even-numbered group region in the buffer in a second direction, and a read module suitable for reading the data of each odd-numbered group region written in the buffer in the second direction and reading the data of each even-numbered group region in the first direction.