DMA Data Writing System with Dual Write Paths
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Solution Overview
Problem
In electronic systems that use direct memory access (DMA) for data transfer, existing methods often require processor occupation for the entire duration of read or write operations, limiting parallel processing and increasing overhead, especially when dealing with large data sets.
Innovation Solution
A data writing system and method that utilize a processing unit, dynamic random access memory (DRAM), and a bus arbiter to execute write transactions through two distinct paths, one passing through a buffer cache and the other bypassing it, allowing for efficient data transfer by determining the number of write transactions to optimize the write process and reduce processor overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred through the buffer cache, then data integrity and caching benefits are improved, but the number of bus arbiter accesses increases (5 times), increasing access time and overhead
Solution Approach 1:
The patent segments the data transfer process into two distinct paths: a first write path through the buffer cache for data requiring caching and integrity verification, and a second write path bypassing the buffer cache for data that does not require caching. This segmentation allows the system to optimize each path independently, reducing unnecessary bus arbiter accesses for non-cached data while maintaining data integrity for cached data.
Solution Approach 2:
The patent applies different transfer characteristics to different portions of data based on their caching requirements. By identifying which data portions benefit from buffer cache storage and which do not, the system applies the appropriate transfer path locally, rather than uniformly applying one path to all data. This reduces overall access time while maintaining data integrity where needed.
2Ease of operation
If the processor handles the entire duration of read or write operations, then data transfer control is simplified, but the processor becomes unavailable for other tasks, reducing system productivity
Solution Approach 1:
The patent extracts the data transfer operation from the processor's direct control by implementing a second write path that bypasses the buffer cache and uses direct memory access. This allows the processor to initiate the transfer and then continue with other tasks, rather than being occupied for the entire duration of the transfer operation, thereby improving system throughput while maintaining adequate control through the bus arbiter.
Solution Approach 2:
The patent introduces the bus arbiter as an intermediary that manages access to the memory interface and coordinates transfers between the processor, buffer cache, and storage device. This intermediary handles the complexity of data transfer operations, allowing the processor to maintain simplified control logic while the bus arbiter manages the actual data movement, enabling parallel processing and improved productivity.
3Stability of the object's composition
If multiple write transactions are executed through the buffer cache, then data consistency is maintained, but power consumption increases due to repeated bus arbiter accesses
Solution Approach 1:
The patent segments the data transfer operations into two categories: those requiring buffer cache mediation for consistency and those that can proceed directly. By identifying and separating these categories, the system maintains data consistency only where necessary while avoiding unnecessary power consumption from repeated bus arbiter accesses for data that does not require consistency verification.
Solution Approach 2:
The patent applies different power efficiency characteristics to different data portions based on their consistency requirements. Data that requires consistency maintenance uses the first write path through the buffer cache with full bus arbiter mediation, while data that does not require consistency uses the second write path that bypasses the buffer cache, significantly reducing power consumption for those portions.
Data Source
AI summary
A data writing system is provided. A processing unit includes at least one core processor. The dynamic random access memory (DRAM) includes a user buffer storing data to be written to a storage device, a buffer cache and a direct memory access (DMA) buffer. The processing unit executes a plurality of write transactions for moving a portion of the data from the user buffer of the DRAM to the storage device via a first write path, and the remainder of the data from the user buffer of the DRAM to the storage device via a second write path. The first write path passes through the buffer cache of the DRAM, and the second write path does not pass through the buffer cache of the DRAM.