Bit-Mapped DMA Dependency Table for Flash IO Latency
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Solution Overview
Problem
Conventional data storage systems require frequent processor intervention for DMA engine operations, leading to inefficient data transfer between memory and the IO bus, as the processor must prepare and enable descriptors between transfer boundaries, interrupting the process and consuming precious processor cycles.
Innovation Solution
Implementing a dependency table that allows DMA engines to manage descriptors and buffer readiness independently, reducing processor intervention by using BufRdy fields to track the status of data buffers and enabling autonomous execution of descriptors, thus minimizing processor involvement in each transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor prepares and enables descriptors between transfer boundaries, then data transfer can be completed, but processor intervention is frequent and consumes precious processor cycles
Solution Approach 1:
The dependency table enables DMA engines to autonomously manage descriptor preparation and buffer readiness tracking without processor intervention. The table stores dependency relationships between descriptors and buffers, allowing DMA engines to self-coordinate transfer operations, thereby freeing the processor from frequent interrupt handling and descriptor setup tasks.
Solution Approach 2:
The dependency table acts as an intermediary data structure that mediates between multiple DMA engines and the processor. It stores index fields representing dependencies between descriptors and buffers, enabling indirect coordination of transfer operations without requiring direct processor involvement in each transfer boundary event.
2Productivity
If two DMA engines operate in parallel utilizing multiple data buffer spaces, then data transfer throughput increases, but processor intervention is required between transfers
Solution Approach 1:
The dependency table implements a feedback mechanism where completion status of buffer transfers is automatically recorded and used to trigger subsequent descriptor execution. Each entry in the dependency table tracks whether a buffer is ready, and this status feedback enables DMA engines to autonomously proceed with dependent transfers without processor polling or intervention.
Solution Approach 2:
The dependency table is pre-configured with dependency relationships between descriptors and buffers before transfer operations begin. This preliminary setup allows DMA engines to execute transfers in the correct sequence based on pre-established dependencies, eliminating the need for processor intervention to coordinate parallel operations as they occur.
3Duration of action of moving object
If the processor is interrupted to prepare the next transfer, then continuous data transfer is maintained, but processor cycles are consumed
Solution Approach 1:
The dependency table enables the DMA subsystem to self-manage continuous transfer operations by automatically tracking buffer readiness and triggering subsequent descriptors. The system serves itself by using the dependency relationships stored in the table to maintain continuous transfer flow without requiring processor interrupts for coordination.
Solution Approach 2:
The dependency table structure allows useful action (data transfer) to continue uninterrupted by enabling DMA engines to autonomously proceed with transfers as buffers become ready. The pre-stored dependency relationships ensure continuous operation without gaps that would require processor intervention to bridge.
Data Source
AI summary
The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptors1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.