DMA Descriptor Branching for Autonomous Transfer Sequences

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Solution Overview

Problem

Current direct memory access (DMA) systems in computer systems require significant CPU involvement for setting up and managing DMA transfers, which can lead to increased overhead and power consumption, especially in scenarios requiring repetitive data transfers.

Innovation Solution

The implementation of DMA descriptors that allow branching decisions, enabling the DMA engine to select among multiple execution paths based on conditional values, thereby reducing CPU involvement and enabling autonomous management of DMA transfer sequences without CPU intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the CPU serves as an intermediary to manage DMA transfers by initiating read and write operations, then data transfer between system memory and peripheral components can be achieved, but CPU overhead increases

Engineering Contradiction:

Improvedata transfer capabilityVSAvoidCPU overhead

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a DMA engine with descriptor-based control that enables autonomous management of data transfer sequences. The DMA engine independently processes descriptors stored in memory, making branching decisions and managing multiple transfer sequences without CPU intervention. This self-service mechanism resolves the contradiction by eliminating the need for CPU to serve as an intermediary, thereby reducing CPU overhead while maintaining full data transfer capability.

Inventive Principle:

Principle #25Self-service

2Productivity

If the CPU manages repetitive data transfers, then data transfer operations can be performed, but power consumption increases

Engineering Contradiction:

Improvedata transfer operationVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The DMA engine with descriptor-based branching control operates autonomously to manage repetitive data transfer sequences. By storing multiple descriptor sequences in memory and enabling the DMA engine to independently select and execute appropriate sequences based on conditional values, the system eliminates the need for CPU involvement in repetitive transfers. This significantly reduces power consumption associated with CPU operation while maintaining full data transfer functionality.

Inventive Principle:

Principle #25Self-service

3Adaptability or versatility

If the DMA engine processes multiple transfer sequences, then transfer flexibility improves, but control complexity increases

Engineering Contradiction:

Improvetransfer sequence flexibilityVSAvoidcontrol mechanism complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces descriptors as an intermediary data structure that stores control information for multiple DMA transfer sequences in memory. The descriptors contain conditional values and linking information that enable the DMA engine to autonomously make branching decisions. This intermediary mechanism provides flexible control over multiple transfer sequences without increasing the complexity of the DMA engine's control logic, as the branching intelligence is embedded in the descriptor data rather than the hardware control circuitry.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9164936B2System and method for regulating direct memory access descriptor among multiple execution paths by using a link to define order of executions

Publication Date: 2015.10.20 SILICON LABORATORIES INC

AI summary

An apparatus includes an integrated circuit that includes a processing core and a direct memory access (DMA) engine. The DMA engine is adapted to process descriptors to control DMA communications. The descriptors contain data indicating communication endpoints that are associated with the DMA communications. The DMA engine is adapted to use other data contained in at least one of the descriptors to control branching of descriptor execution among multiple execution paths.