DMA Circuit Descriptor Pointer Verification for Data Integrity

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Solution Overview

Problem

Existing DMA circuits lack sufficient protection for descriptors during data transfer, leading to potential incorrect addressing and data corruption due to address line failures between the memory controller and memory, which can result in inaccurate data transfer.

Innovation Solution

A DMA circuit with registers for storing top and bottom pointers of descriptors, a transfer circuit for reading and analyzing descriptors, and a comparison circuit to verify descriptor pointers, ensuring accurate data transfer by detecting and preventing incorrect addressing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If DMA circuit performs data transfer without descriptor verification, then data transfer speed is maintained, but data integrity deteriorates due to address line failures

Engineering Contradiction:
Improvedata integrityVSAvoidDMA circuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by verifying descriptor pointers before data transfer execution. The comparison circuit checks whether the descriptor pointer matches the bottom pointer value before the transfer circuit reads data from memory, preventing incorrect data transfer due to address line failures. This pre-verification mechanism ensures data integrity without requiring complex error correction during transfer.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a comparison circuit as an intermediary between the transfer circuit and memory. This intermediary component verifies the descriptor pointer validity by comparing it with the bottom pointer value, acting as a mediator that prevents incorrect memory access without adding complex error correction mechanisms to the main transfer path.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If DMA circuit includes pointer verification mechanism, then address failure detection improves, but processing time increases due to additional comparison operations

Engineering Contradiction:
Improveaddress accuracyVSAvoiddescriptor verification time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by performing verification only on critical pointer values (descriptor pointer and bottom pointer) rather than validating entire descriptor structures. This selective verification approach provides sufficient address accuracy protection while minimizing the time overhead compared to comprehensive descriptor validation.

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If DMA circuit uses simple transfer mechanism without verification, then device complexity is reduced, but harmful factors increase due to undetected address errors

Engineering Contradiction:
Improvecircuit structureVSAvoiddata corruption risk
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a comparison circuit as an intermediary component that verifies descriptor pointer validity before data transfer. This intermediary provides error detection protection against data corruption while adding only minimal circuit complexity, as it performs simple pointer value comparison rather than comprehensive error correction.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The DMA circuit performs self-verification by comparing its own descriptor pointer against the stored bottom pointer value. This self-service mechanism enables the circuit to detect address errors autonomously without requiring external verification systems, balancing simplicity with error detection capability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7552249B2Direct memory access circuit and disk array device using same
Publication Date: 2009.06.23 FUJITSU LTD
  • US7552249B2 patent drawing
  • US7552249B2 patent drawing
  • US7552249B2 patent drawing

AI summary

A DMA circuit prevents an erroneous data transfer by a descriptor due to an address failure of memory. When a descriptor is created, the data processing unit writes a pointer, for storing the descriptor, in a predetermined part of the descriptor, and stores the descriptor in memory, and when a DMA engine reads the descriptor from the memory, the DMA engine confirms whether the value is correct, and judges whether a DMA transfer of the data in the memory is possible. For both reading and writing of a descriptor, data corruption due to an address failure can be prevented.