Descriptor Prefetch Mechanism for High Latency DMA Systems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High latency environments in DMA systems lead to data bus stalls and inefficiencies due to the need for sequential descriptor fetching and processing, which is not effectively managed by existing DMA controllers.
Innovation Solution
A DMA device with a descriptor prefetch buffer that assumes sequential descriptor storage, prefetches multiple descriptors, and discards non-sequential ones, maintaining a full buffer by requesting additional descriptors whenever possible, and using an aggressive prefetch in high latency conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If descriptors are fetched sequentially from memory in a high latency environment, then the DMA device can process descriptors in order, but data bus stalls occur and transfer efficiency decreases
Solution Approach 1:
The patent implements a descriptor prefetch buffer that fetches multiple descriptors from memory in advance before they are needed for processing. The DMA device proactively loads descriptors into the prefetch buffer during idle periods or in parallel with data transfers, so that when a descriptor is needed for processing, it is already available in the buffer rather than waiting for memory fetch. This preliminary action eliminates data bus stalls and maintains continuous operation, resolving the contradiction between processing correctness and transfer efficiency.
2Reliability
If the DMA device waits for descriptor memory operations to complete before starting data block moves, then configuration registers are properly updated, but overlapping operations cannot occur and throughput is reduced
Solution Approach 1:
The patent separates the descriptor fetch operation from the data block move operation by introducing a dedicated prefetch buffer. Descriptors are fetched into the buffer independently of the data transfer operations. The DMA device can then process descriptors from the buffer while simultaneously performing data block moves, allowing overlapping of configuration updates and data transfers. This segmentation resolves the contradiction by enabling both reliable register updates and high throughput operations to occur in parallel.
3Adaptability or versatility
If the DMA device uses a linked list architecture for flexibility, then dynamic descriptor management is enabled, but sequential access assumptions may be violated causing processing delays
Solution Approach 1:
The prefetch buffer pre-loads multiple descriptors from the linked list into contiguous buffer slots in advance. Even though the linked list may have non-sequential memory addresses, the prefetch mechanism fetches multiple descriptors proactively before they are needed. This preliminary action compensates for the non-sequential nature of linked lists, ensuring that descriptors are ready for processing without delays. The buffer acts as a buffer against the irregular access patterns inherent in linked list structures, maintaining both flexibility and timing efficiency.
Data Source
AI summary
A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and discards any descriptors that are found to violate this assumption. The DMA engine seeks to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine fetches these descriptors from system memory and writes them to the prefetch buffer. The DMA engine may also use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any space in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.