DMA Descriptor Queue Read Pointer Derivation

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Solution Overview

Problem

Existing network interface devices require significant storage space for address pointers to manage DMA command queues, especially in systems with multiple physical ports, leading to inefficient use of integrated circuit chip resources.

Innovation Solution

Implementing a mechanism to algorithmically derive write addresses in local stores from read pointers for corresponding DMA command queues in host memory, eliminating the need for separate write pointers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If separate write pointers are maintained for each local store in multiple DMA command queues, then address management is simplified and direct, but storage space requirements on the integrated circuit chip increase significantly

Engineering Contradiction:
Improveaddress managementVSAvoidstorage space for address pointers
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent merges the write pointer functionality into the read pointer by deriving the write address algorithmically from the read pointer value. Instead of maintaining separate write and read pointers, the system uses a single read pointer and calculates the write address through address wrapping logic, where the write address is derived by taking the read pointer value and applying modulo arithmetic with respect to the local store size.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The read pointer is given a dual function: it serves both as the read address pointer and as the basis for generating write addresses. The same pointer value is used to identify both the current read location in host memory and, through algorithmic derivation, the corresponding write location in local store memory, eliminating the need for dedicated write pointer storage.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple physical ports are supported with separate DMA command queues, then network interface versatility is improved, but the storage space for address pointers increases proportionally

Engineering Contradiction:
Improvemulti-port supportVSAvoidstorage space for address pointers
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

For each physical port's DMA command queue, the patent combines the read and write pointer functions into a single read pointer mechanism. Each queue maintains one read pointer in host memory, and the corresponding local store derives its write address from this same read pointer value through address wrapping, reducing the pointer storage requirement from two pointers per queue to one pointer per queue.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the parameter representation by transforming the write pointer from a directly stored value into a derived value based on the read pointer. The write address parameter is no longer independently stored but is instead generated through parameter transformation using the read pointer value and the local store size as the transformation basis.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP1896965B1DMA descriptor queue read and cache write pointer arrangement
Publication Date: 2010.07.14 SOLARFLARE COMMUNICATIONS INC
  • EP1896965B1 patent drawingFigure 1
  • EP1896965B1 patent drawingFigure 2
  • EP1896965B1 patent drawingFigure 3

AI summary

Method and apparatus for retrieving buffer descriptors from a host memory for use by a peripheral device. In an embodiment, a peripheral device such as a NIC includes a plurality of buffer descriptor caches each corresponding to a respective one of a plurality of host memory descriptor queues, and a plurality of queue descriptors each corresponding to a respective one of the host memory descriptor queues. Each of the queue descriptors includes a host memory read address pointer for the corresponding descriptor queue, and this same read pointer is used to derive algorithmically the descriptor cache write addresses at which to write buffer descriptors retrieved from the corresponding host memory descriptor queue.