DMA Descriptor Scheduling for Real-Time Data Transfer
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Solution Overview
Problem
In real-time systems, existing methods for data transfer between tasks using a direct memory access (DMA) controller are inefficient for small data sizes and require complex resource management, potentially leading to processor overload and data integrity issues.
Innovation Solution
A method involving the creation of DMA descriptors to manage data transfers between real-time tasks, sorted by visibility dates or deadlines, with a DMA controller processing these descriptors to optimize data transfer scheduling and secure memory access through hardware protection mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfers are delegated to a DMA controller, then processor time is released for application processing, but the fixed initial cost of DMA setup becomes inefficient for very small data sizes
Solution Approach 1:
The patent changes the parameter of DMA transfer size by coalescing multiple small data transfers into larger contiguous memory operations. The DMA controller is configured to accumulate small data items from different tasks into a single larger transfer operation, thereby reducing the fixed initial cost overhead per byte transferred while maintaining processor availability for application processing.
2Productivity
If a DMA controller is used for data transfers, then data transfer efficiency improves, but complex resource management and coordination between DMA and processor are required
Solution Approach 1:
The patent introduces a buffer memory as an intermediary between the DMA controller and the processor. Small data transfers from multiple tasks are first accumulated in this buffer memory by the DMA controller, and then a single coalesced transfer operation moves the aggregated data to the destination. This intermediary structure simplifies resource management by decoupling the frequent small transfers from the processor while maintaining efficient bulk transfer operations.
3Speed
If DMA controller is used for inter-task communications, then data transfer speed improves, but data integrity issues may occur due to concurrent memory access by processor and DMA
Solution Approach 1:
The patent implements preliminary action by having the DMA controller accumulate and coalesce small data transfers into a single larger transfer operation before executing the actual memory transfer. This preliminary coalescing phase allows the system to plan and coordinate the memory access pattern in advance, reducing the risk of data integrity issues by minimizing the number of concurrent access points and establishing a predictable transfer sequence before execution.
Data Source
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AI summary
The invention relates to a method for transferring at least one data item between a real-time task producing a data item (20) and a real-time task (21) consuming said data item, each data item being associated with a visibility date, the method being performed in a computer (10) including a central memory (4), at least one processor (2) and at least one direct memory access (DMA) controller (3), each DMA controller (3) being configured to support data transfers between various zones of the central memory (4),controlled by an operating system (200) running on the processors (2), characterised in that said method includes the following steps, in response to the initiation of the data transfer by the running instance k of an initiating task (20, 21): the operating system (200) creating (301) at least one DMA descriptor to describe the transfer by DMA expected for said data item, after executing a given instance (k-1 or k) of the task; said operating system (200) inserting (302) the DMA descriptors into a list of descriptors (26) to be processed by said DMA controller (3), said DMA descriptors being inserted in a sorted manner according to a sorting criterion related to the visibility date of the data and/or of the time behaviour of the tasks; processing the descriptors of the list of DMA descriptors (26) by executing DMA requests (303) by the DMA controller (3); and the operating system (200) executing the subsequent instance (k or k+1) of the initiating task, depending on the end of the processing of a predefined set of DMA descriptors of the list of descriptors.