DMA Descriptor Skip Control for High-Speed Data Transfer
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Solution Overview
Problem
Existing DMA transfer methods require reading descriptor information for all frames, even if not all can be transferred in a single activation, leading to unnecessary time consumption when multiple frames are untransferable.
Innovation Solution
A data transfer device with a descriptor information storage part, a read part, a transfer determination part that counts read descriptor information and outputs a backward skip instruction when the transferable frame count is reached, and a data transfer part that skips reading remaining descriptor information upon receiving this instruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the descriptor information of all frames is read sequentially to determine transferability, then the transfer determination accuracy is improved, but the transfer time increases due to reading unnecessary descriptor information for untransferable frames
Solution Approach 1:
The patent applies the skipping principle by allowing the descriptor information read part to skip reading remaining descriptor information when a backward skip instruction is output. This enables the system to rush through the unnecessary reading of untransferable frame descriptors, thereby reducing transfer time while maintaining accurate transfer determination through the count-based control mechanism.
Solution Approach 2:
The patent implements preliminary action by counting the number of descriptor information pieces read and comparing it with the transferable frame count before completing the reading process. This preliminary count-based determination allows the system to decide in advance whether to continue reading or skip to the end, preventing the time loss that would occur from reading all descriptor information sequentially.
2Productivity
If the entire descriptor chain is transferred by a single activation, then the productivity is improved, but this is limited by the predetermined transferable frame count
Solution Approach 1:
The patent applies dynamics by implementing a hybrid transfer mechanism that adapts to the descriptor chain length. When the descriptor chain length is within the transferable frame count, the system performs a single activation transfer to maximize productivity. When the descriptor chain exceeds the transferable frame count, the system dynamically switches to multiple activations with backward skip instructions, maintaining adaptability while preserving high-speed transfer capabilities for eligible frames.
3Adaptability or versatility
If multiple activations are used to transfer descriptor chains exceeding the transferable frame count, then the adaptability is improved, but the transfer time increases due to repeated reading operations
Solution Approach 1:
The patent applies skipping by enabling the descriptor information read part to skip reading remaining descriptor information in subsequent activations after the first activation reads up to the transferable frame count. This eliminates the need to repeatedly read the same descriptor information in multiple activations, significantly reducing transfer time while maintaining the adaptability to handle descriptor chains of any length through multiple activations.
Data Source
AI summary
A data transfer device performing data transfer at a high speed if a descriptor chain cannot be entirely transferred by a single activation. In a DMA control device, when a transfer activation signal is asserted, a descriptor information control part sequentially reads descriptor information from a descriptor information storage part. When the count of pieces of descriptor information that have been read becomes equal to a transferable frame count, a backward skip control part outputs a backward skip instruction. When the backward skip instruction is outputted, a descriptor information control part skips reading remaining descriptor information.