DMA Engine Audio Video Transfer Interrupt Reduction
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Solution Overview
Problem
Standard DMA techniques for data transfer over serial buses, such as USB, often result in an excessive number of interrupts, which can hinder efficient processing and operation, particularly in devices handling audio and video data.
Innovation Solution
A method employing a DMA engine that provides audio and video data packets with the same destination addresses, coupled with data storage logic using circular buffers and programmable hardware elements like FPGAs, to reduce interrupts and enhance data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard DMA techniques are used for data transfer over serial bus, then data transfer can be performed, but an excessive number of interrupts occur which hinders efficient processing
Solution Approach 1:
The patent combines multiple data packets into a single DMA transfer operation by using a ring buffer structure. Instead of processing each packet individually which generates separate interrupts, the system accumulates multiple packets in the ring buffer and processes them together, thereby reducing the total number of interrupts while maintaining data transfer efficiency
Solution Approach 2:
The system performs preliminary actions by pre-allocating ring buffers and setting up DMA descriptors in advance. The ring buffer structure is prepared beforehand with predetermined memory locations, allowing the DMA engine to operate continuously without frequent interrupt interruptions for memory management, thus reducing interrupt overhead
Data Source
AI summary
DMA transfer of audio and video data. The audio and video data may be received over a serial bus. A DMA engine may provide audio and video data packets to data storage logic based on the audio and video data. The DMA engine may provide each of the audio data packets with a first, same destination address of a first memory and may provide each of the video data packets with a second, same destination address of the first memory. The data storage logic may maintain first and second pointers that indicate a next current memory location for audio data in a first buffer and video data in a second buffer in the first memory, respectively. The data storage logic may receive and store the audio and video data packets at respective locations in the first and second buffers based on current values of the first and second pointers.