DMA Engine Bitmap Manipulation Near-Memory Compute
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Solution Overview
Problem
Traditional software-focused implementations for bitmap manipulation in cache-based architectures lead to performance inefficiencies, particularly in artificial intelligence computing graph analytics on larger sparse datasets, due to low spatial and temporal locality of randomly accessed sparse data, resulting in increased cache misses and reduced performance.
Innovation Solution
The technology provides a direct memory access (DMA) instruction set architecture (ISA) with near-memory compute capability and hardware support for bitmap operations, such as finding the first set bit, bitmap gather, scatter, and population count, implemented in a 64-bit Distributed Global Address Space system with pipeline-local DMA engines and atomic lock buffers to enhance efficiency and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-focused implementations are used for bitmap manipulation in cache-based architectures, then ease of operation is maintained, but productivity deteriorates due to low spatial and temporal locality of randomly accessed sparse data resulting in increased cache misses
Solution Approach 1:
The patent introduces a DMA engine as an intermediary component between the processor and memory system. The DMA engine executes bitmap manipulation operations directly in memory without requiring data to be transferred to processor caches, thereby eliminating cache miss latency while maintaining software-level control through programmed DMA operations.
Solution Approach 2:
The patent replaces the traditional software-based bitmap manipulation mechanism (which relies on processor caches and sequential instruction execution) with a hardware-based DMA engine that performs operations directly in memory. This substitution eliminates the mechanical bottleneck of cache-based processing and enables parallel execution of bitmap operations.
2Productivity
If traditional cache-based architectures are used for bitmap operations, then device complexity is avoided, but productivity deteriorates due to increased cache misses from random access patterns
Solution Approach 1:
The DMA engine is designed as a universal processing unit that can handle multiple bitmap manipulation operations (gather, scatter, population count, find first bit set) within a single memory system architecture. This multi-functionality enables the same hardware component to serve various bitmap operations without requiring separate specialized units for each operation type.
3Loss of time
If software-focused implementations are used, then ease of manufacture is maintained, but loss of time increases due to extra network traversals in distributed memory systems
Solution Approach 1:
The DMA engine acts as an intermediary that performs bitmap operations locally within the memory system before results need to be communicated over the network. By executing operations such as population count and gather/scatter locally, the system reduces the volume of data that must traverse the network, thereby eliminating network traversal latency while maintaining a relatively simple implementation through standard DMA architecture.
Data Source
AI summary
Systems, apparatuses and methods may provide for technology that detects, by an operation engine, a plurality of sub-instruction requests from a first memory engine in a plurality of memory engines, wherein the plurality of sub-instruction requests are associated with a direct memory access (DMA) bitmap manipulation request from a first pipeline, wherein each sub-instruction request corresponds to a data element in the DMA bitmap manipulation request, and wherein the first memory engine is to correspond to the first pipeline. The technology also detects, by the operation engine, one or more arguments in the plurality of sub-instruction requests, sends, by the operation engine, one or more load requests to a DRAM in the plurality of DRAMs in accordance with the one or more arguments, and sends, by the operation engine, one or more store requests to the DRAM in accordance with the one or more arguments, wherein the operation engine is to correspond to the DRAM.