DMA Engine Delay Circuitry for Flexible Transfer Control
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Solution Overview
Problem
Existing DMA systems face challenges in managing completion delays for off-chip transfers, often resulting in performance inefficiencies due to either unnecessarily long delays or reduced flexibility in allocating transfers to contexts with varying latency.
Innovation Solution
A DMA engine with delay circuitry that allows per-descriptor control of completion delays, enabling flexible management of delays based on indications in descriptors, thereby reducing CPU involvement and performance costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed predetermined completion delay is used for all transfers, then reliability is improved by ensuring sufficient delay for off-chip transfers, but productivity deteriorates due to unnecessarily long delays for transfers that don't require maximum delay
Solution Approach 1:
The patent applies parameter changes by making the completion delay variable rather than fixed. Each descriptor can specify a different completion delay value based on the specific transfer requirements. This allows the system to use minimal necessary delay for each transfer, improving throughput while maintaining reliability when needed.
Solution Approach 2:
The patent implements dynamics by allowing the completion delay to be dynamically adjusted per transfer through descriptor configuration. The delay circuitry responds to individual transfer characteristics rather than applying a static delay to all transfers, enabling optimal performance for each specific operation.
2Adaptability or versatility
If multiple contexts with different completion delays are provided, then adaptability is improved for handling different off-chip timing requirements, but device complexity increases due to additional contexts and restricted transfer allocation
Solution Approach 1:
The patent applies local quality by allowing each descriptor to have its own completion delay parameter tailored to specific transfer requirements. This eliminates the need for multiple global contexts with fixed delays, as each transfer can be locally configured with appropriate delay characteristics.
Solution Approach 2:
The patent implements universality by creating a single DMA context that can handle transfers with varying completion delays through descriptor-based configuration. This multi-functional approach replaces multiple specialized contexts, reducing device complexity while maintaining adaptability.
3Adaptability or versatility
If programmable completion delay is allowed for each context, then adaptability is improved, but ease of operation deteriorates due to requiring CPU reprogramming cycles
Solution Approach 1:
The patent applies preliminary action by pre-configuring completion delay values directly in the descriptors during transfer setup. This eliminates the need for runtime CPU reprogramming of context registers, as the delay parameters are already embedded in the transfer descriptors when they are created.
Solution Approach 2:
The patent implements self-service by allowing the descriptor to carry its own completion delay configuration. The DMA engine automatically uses the delay value specified in each descriptor without requiring CPU intervention to program context-specific delay registers, reducing CPU involvement while maintaining adaptability.
Data Source
AI summary
A circuit comprising: an execution unit; a plurality of addressable devices; and a data transfer engine coupled to the execution unit and to the devices, operable to fetch a plurality of descriptors under control of the execution unit, and based on each of the fetched descriptors to perform a transfer of data from a respective first to a respective second of the devices. The DMA engine comprises delay circuitry operable to block, during a delay period running from an earlier of the transfers, any later of the transfers involving at least one of the same devices as the earlier transfer, the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors.