Single DMA Engine with Independent Caches for HPC NIC State Management
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Solution Overview
Problem
In high performance computing systems, processing messages by the Network Interface Controller (NIC) increases communication time and die size due to the need for additional resources to manage application state, which is not efficiently managed with multiple independent DMA engines and redundant data paths.
Innovation Solution
Implementing a single DMA engine with multiple contexts to manage all message classes, reducing redundant data paths and optimizing arbitration, and using independent caches for virtual to physical address translation to accelerate message processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple independent DMA engines are used to process messages, then message processing capability is improved, but die size increases due to redundant data paths
Solution Approach 1:
The patent consolidates multiple independent DMA engines into a single DMA engine that handles multiple message classes. This merging eliminates redundant data paths and reduces die size while maintaining message processing capability through shared resources and contexts.
Solution Approach 2:
The single DMA engine is designed with multi-functionality to handle multiple message classes through context switching. It can be configured to process different types of messages (isochronous, interrupt, data, control) by loading appropriate contexts, replacing the need for dedicated engines for each message type.
2Productivity
If additional resources are added to the NIC to manage application state, then message processing by NIC is improved, but communication time increases
Solution Approach 1:
The patent pre-allocates and manages application state resources (descriptors, buffers, contexts) in advance within the NIC. By having these resources prepared and managed locally in the NIC rather than requiring host processor intervention during message processing, communication time is reduced while maintaining improved message processing capability.
3Area of stationary object
If a single DMA engine with multiple contexts is used, then die size is reduced by eliminating redundant paths, but device complexity increases
Solution Approach 1:
The patent segments the single DMA engine into multiple independent contexts, where each context can be configured to handle specific message classes. This segmentation allows the engine to function independently for each message type while sharing common hardware resources, reducing die size while managing complexity through modular context structures.
Data Source
AI summary
Methods related to communication between and within nodes in a high performance computing system are presented. Processing time for message exchange between a processing unit and a network controller interface in a node is reduced. Resources required to manage application state in the network interface controller are minimized. In the network interface controller, multiple contexts are multiplexed into one physical Direct Memory Access engine. Virtual to physical address translation in the network interface controller is accelerated by using a plurality of independent caches, with each level of the page table hierarchy cached in an independent cache. A memory management scheme for data structures distributed between the processing unit and the network controller interface is provided. The state required to implement end-to-end reliability is reduced by limiting the transmit sequence number space to the currently in-flight messages.