DMA Engine Logical Addressing Concurrent Memory Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current DMA technologies face challenges in efficiently managing context switching between partial transfers using different Scatter/Gather Lists (SGLs), particularly in supporting concurrent and random partial transfers, due to their reliance on physical addressing and shared system bus architectures, which limits performance and concurrency.
Innovation Solution
The implementation of a logical addressing and address translation method using a switch fabric design with a read port arbiter and write port logic, along with a Buffer State Table (BST) to treat each logical data buffer as an independent linear space, enabling non-blocking concurrent operations and supporting random and sequential mapping across multiple memory spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If physical addressing and shared system bus architecture are used, then device compatibility is maintained, but concurrency and data transfer throughput are limited
Solution Approach 1:
The patent introduces a Buffer State Table (BST) as an intermediary data structure between the logical address space and physical scatter/gather buffers. The BST maintains mapping relationships and transfer states, enabling the DMA controller to manage multiple concurrent transfers with logical addresses without directly handling complex physical address calculations and context switching between different scatter/gather lists.
Solution Approach 2:
The patent segments the address management function into two independent layers: logical address space management handled by the BST and physical address translation handled by the scatter/gather list structure. This segmentation allows concurrent operations on logical addresses while physical address translation occurs independently, removing the bottleneck of context switching between partial transfers.
2Adaptability or versatility
If context switching between partial transfers using different SGLs is implemented, then flexible data transfer is enabled, but processing overhead increases
Solution Approach 1:
The patent creates a virtual copy of the scatter/gather buffer structure in the form of the Buffer State Table, which mirrors the essential information (buffer addresses, lengths, transfer positions) needed for context management. This copying approach allows the system to track multiple buffer states simultaneously without actually switching between physical scatter/gather list contexts, eliminating the overhead of context switching while maintaining flexible data transfer capabilities.
3Productivity
If shared system bus architecture is used, then hardware compatibility is maintained, but concurrent access to memory spaces is blocked
Solution Approach 1:
The patent transitions from a single-dimension shared bus architecture to a multi-dimensional address space model using the Buffer State Table. The BST enables independent logical address spaces that can be accessed concurrently, effectively adding a dimension of parallelism by decoupling logical address management from physical bus arbitration. This allows multiple DMA channels to operate independently on different logical buffers simultaneously, even over a shared physical bus.
Data Source
AI summary
A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.