DMA Engine Network Access to Reduce Remote Memory Latency

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Solution Overview

Problem

Scale-out and distributed architectures with disaggregated memory resources face increased latency due to remote memory access across network elements, leading to inefficiencies in data transmission and resource utilization.

Innovation Solution

A data center architecture utilizing chassis-less sleds with optical interconnects and independent resource allocation, enabling efficient and flexible management of compute, memory, and storage resources, reducing latency through direct memory access (DMA) engines and network interfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory pools are located remote from compute nodes in disaggregated memory architectures, then resource utilization and scalability are improved, but access latency increases due to packet formation, processing, and media traversal across network elements

Engineering Contradiction:
Improveresource utilizationVSAvoidaccess latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system segments memory resources from compute nodes into separate memory pools, allowing independent management and allocation. This segmentation enables improved resource utilization by allowing memory to be shared across multiple compute nodes while the DMA engine handles the complexity of remote access transparently

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The DMA engine acts as an intermediary between compute nodes and remote memory pools. It handles packet formation, network communication, and data transfer operations, shielding compute nodes from the latency overhead of remote memory access while enabling efficient data movement between distributed memory resources

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If chassis-less sleds with independent resource allocation are used, then ease of upgrades and thermal cooling are improved, but device complexity increases due to separate management of compute, memory, and storage resources

Engineering Contradiction:
Improveease of upgradesVSAvoiddevice complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The system divides the computing platform into separate chassis-less sleds, each dedicated to specific functions (compute, memory, storage, or networking). This physical segmentation allows independent upgrades of individual sleds without affecting other components, simplifying maintenance and upgrades while managing complexity through functional separation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The DMA engine provides universal functionality across different sled types and memory access patterns. It handles both local and remote memory access, supports various network protocols, and manages data transfers between different sled configurations, reducing the complexity burden of heterogeneous resource management

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12381751B2Direct memory access (DMA) engine with network interface capabilities
Publication Date: 2025.08.05 INTEL CORP
  • US12381751B2 patent drawing
  • US12381751B2 patent drawing
  • US12381751B2 patent drawing

AI summary

Examples described herein include one or more processors; a network interface; and a direct memory access (DMA) engine communicatively coupled to the one or more processors. In some examples, the DMA engine is to receive a DMA data access request and based on an address in the DMA data access request corresponding to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device. In some examples, if the source address corresponds to a local memory device and the destination address corresponds to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device.