DMA Engine Synchronization via EOT Counter for Non-Uniform Memory Architecture
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Solution Overview
Problem
Existing data transfer methods between multiple independent memory controllers in storage servers face challenges in ensuring synchronization across nodes without requiring special synchronization features on communication links, leading to potential data inconsistencies and inefficiencies.
Innovation Solution
The implementation of a DMA engine that sends End of Transfer (EOT) messages with synchronization flags, allowing nodes to wait for acknowledgement before processing subsequent control blocks, ensuring that data writes are correctly ordered and synchronized across nodes, even over varied communication links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DMA engine sends EOT messages with synchronization flags and waits for acknowledgements, then data synchronization reliability is improved, but processing time increases due to waiting for EOT counter to return to zero
Solution Approach 1:
The system implements feedback through EOT acknowledgements from the receiving node to the sending DMA engine. The receiving node sends EOT acknowledgements back to confirm receipt of data, and the DMA engine uses this feedback to determine when the EOT counter returns to zero, enabling synchronized processing across nodes while maintaining data reliability.
Solution Approach 2:
The EOT counter acts as an intermediary mechanism that mediates between the sending DMA engine and receiving node. It tracks the state of data transfers and synchronization flags, coordinating the timing of control block processing without requiring direct continuous communication between nodes, thus balancing reliability and processing efficiency.
2Productivity
If nodes use multiple independent memory controllers for parallel data transfer, then productivity is improved, but data consistency becomes difficult to maintain across controllers
Solution Approach 1:
The system segments data transfers into discrete control blocks, each with its own EOT message and synchronization flag. This allows multiple independent memory controllers to process different control blocks in parallel while maintaining individual accountability for each transfer, ensuring data consistency across parallel operations.
Solution Approach 2:
The sending node preliminarily marks control blocks with synchronization flags before transmission. This preliminary action enables the receiving node to identify which transfers require synchronization, allowing parallel processing of non-synchronized blocks while ensuring consistency for synchronized blocks through the EOT acknowledgement mechanism.
Data Source
AI summary
A first node includes a DMA engine for transferring data specified by a sequence of control blocks to a second node. When a control block does not require synchronization between memories, the DMA engine sends an end of transfer (EOT) message after the last datum, increments an EOT counter, and processes the next control block. When a control block requires synchronization and the EOT counter is at zero, the DMA engine sends an EOT with a flag after the last datum, increments the EOT counter, and waits for the EOT counter to return to zero before processing the next control block. A memory controller at the second node detects the EOT with or without a flag and generates an EOT acknowledgement with or without a flag. When a link interface at the second node detects the EOT acknowledgement with a flag, it sends an interrupt to a local processor complex.