DMA Flow Control Circuit Token Protocol Buffer Management
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Solution Overview
Problem
Direct memory access (DMA) transfers can lead to buffer underflow or overflow issues due to unregulated data flow, causing invalid data or interconnect blockages, as DMA controllers initiate transfers without feedback from devices.
Innovation Solution
A DMA circuit with a flow control circuit that manages token counts for each data channel, enabling or disabling transfers based on token availability, and a transfer control circuit that performs transfers only when enabled, storing requests when disabled, to regulate DMA transfers and prevent buffer overflow/underflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DMA transfers are performed without flow control, then data transfer speed is improved, but buffer overflow or underflow occurs causing data integrity issues
Solution Approach 1:
The patent implements a feedback mechanism where the flow control circuit receives token counts from the device, which reflect the current buffer status. This feedback loop allows the DMA controller to adjust its transfer behavior dynamically, enabling high-speed transfers when buffers have capacity while preventing overflow or underflow when buffers are full or empty, thus resolving the contradiction between speed and data integrity
Solution Approach 2:
The patent introduces an intermediary flow control circuit that sits between the DMA controller and the device. This intermediary translates device buffer status (via token counts) into transfer enable/disable signals, mediating the interaction between the high-speed DMA engine and the device's buffer capacity constraints, thereby maintaining both speed and reliability
2Reliability
If flow control is implemented to prevent buffer overflow/underflow, then data integrity is improved, but transfer requests are delayed when tokens are unavailable
Solution Approach 1:
The patent employs preliminary action by having the flow control circuit continuously monitor token counts and maintain a ready state for transfers. When tokens are available, transfers can proceed immediately without delay. The system prepares in advance by tracking buffer status, so when data is ready to be transferred, the path is already cleared, minimizing latency while maintaining reliability
Solution Approach 2:
The patent changes the operational parameter of the DMA controller from a static enable/disable state to a dynamic state based on token count thresholds. By adjusting the transfer enable parameter according to real-time token availability, the system optimizes the balance between preventing buffer errors and minimizing transfer delays, allowing rapid resumption of transfers as soon as tokens become available
3Productivity
If DMA controller initiates transfers autonomously, then transfer efficiency is improved, but buffer overflow or underflow occurs due to lack of device feedback
Solution Approach 1:
The patent implements feedback by having the device provide token count information to the flow control circuit, which then informs the DMA controller's transfer decisions. This feedback mechanism allows the autonomous DMA controller to operate efficiently while being guided by real-time buffer status information, preventing buffer overflow or underflow without requiring constant device intervention in the transfer initiation process
Solution Approach 2:
The patent applies self-service by enabling the DMA controller to autonomously make transfer decisions based on the token count information it receives. The flow control circuit processes the device's buffer status and automatically enables or disables transfers without requiring direct device involvement in each transfer decision, maintaining transfer efficiency while ensuring buffer safety through the automated feedback-driven control
Data Source
AI summary
Circuits and methods are disclosed that allow devices to control the flow of DMA transfers to or from the devices using a token based protocol. In one example implementation, a DMA circuit includes a transfer control circuit that performs data transfers over a first data channel of a device, when transactions on the first data channel are enabled. The DMA circuit includes a flow control circuit that increments a token count for a data channel of a device when a token for the data channel is received and decrements the token count for each data transfer on the data channel performed by the DMA circuit. The flow control circuit enables data transfers on the data channel when the token count is greater than 0, and otherwise, disables data transfers on the data channel.