DMA Control Device Immediate Value Mode for Register Access

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Solution Overview

Problem

Existing DMA control technologies face challenges in reducing the number of processing cycles and power consumption when dealing with discontiguous register addresses, particularly during frequent tasks involving writing to or reading from peripheral circuit registers.

Innovation Solution

The implementation of a DMA control device with basic-function setting registers and scatter-gather setting registers, where the DMAC_SRC register can be used as an immediate-value register, allowing direct specification of data without reading from memory, and the DMAC_SCATTER register enables efficient task execution by setting operation modes for multiple tasks using fewer bus accesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If the DMAC executes writing to or reading from each register as one task using conventional scatter-gather mode, then the peripheral circuits can be controlled without CPU intervention, but the number of processing cycles increases and power consumption increases due to discontiguous addresses

Engineering Contradiction:
ImproveCPU interventionVSAvoidpower consumption
Core Design Contradiction:
Extent of automationVSUse of energy by stationary object

Solution Approach 1:

The patent segments the task execution process by introducing a flag register that divides tasks into two types: those requiring memory reading (conventional scatter-gather) and those using immediate values (new mode). This segmentation allows selective optimization for register access tasks, reducing unnecessary memory bus accesses and lowering power consumption while maintaining automation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the operational parameter of the DMAC by adding a new mode bit in the flag register. When this bit is set to '1', the DMAC operates in immediate value mode for scatter-gather tasks, directly using the address from the scatter-gather register without reading from memory. This parameter change eliminates redundant bus accesses and reduces power consumption for frequent register operations.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If the DMAC executes writing to or reading from each register as one task, then each register access can be performed individually, but the number of processing cycles increases

Engineering Contradiction:
Improveregister accessVSAvoidprocessing cycles
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-loading the register address and value into the scatter-gather register before task execution. When the immediate value mode is activated, the DMAC directly uses these pre-loaded values without requiring runtime memory reads. This preliminary preparation reduces the number of processing cycles during actual task execution while maintaining ease of operation.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If a task of performing writing to or reading from a register only once is executed, then the task can be performed with minimal operations, but it is difficult to reduce the number of processing cycles when using reference address and relative address methods

Engineering Contradiction:
Improvetask execution efficiencyVSAvoidaddress management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the address management complexity by separating immediate value tasks from conventional scatter-gather tasks. By using the flag register to identify immediate value tasks, the system eliminates the need for complex reference address and relative address calculations for single-register operations. This extraction simplifies address management while improving task execution efficiency for frequent register accesses.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10031871B2DMA control device, micro control unit, and DMA control method
Publication Date: 2018.07.24 FUJITSU LTD
  • US10031871B2 patent drawing
  • US10031871B2 patent drawing
  • US10031871B2 patent drawing

AI summary

A direct memory access (DMA) control device including: a basic-function setting register used to perform DMA operation; and a scatter-gather setting register in which a value indicating that a task is executed through setting of a directly defined value for data to be written to the basic-function setting register without reading the data from a memory through a bus is set.