DMA Integrity Checker Autonomous Error Detection
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Solution Overview
Problem
DMA controllers can cause havoc in digital systems if they inadvertently act on corrupted data stored in memory, and they consume microprocessor resources for managing data transfers.
Innovation Solution
Implementing improved DMA integrity checking techniques by programming the DMA controller with transaction control sets and corresponding error detection coding information, where the actual error detection code is incrementally updated during data transfers and checked against expected codes to ensure data integrity, allowing autonomous operation without microprocessor intervention when no errors are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DMA controller operates autonomously without microprocessor intervention, then productivity is improved, but reliability deteriorates due to potential corruption of data by corrupted memory bits
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing expected error detection codes in the DMA controller before data transfers occur. These codes are computed based on the transaction control sets and stored in memory, allowing the DMA to autonomously verify data integrity during transfers without microprocessor intervention. This preparatory measure enables the DMA to detect corrupted memory bits independently, resolving the contradiction between autonomous operation and data reliability.
2Reliability
If error detection codes are checked at every transaction control set, then reliability is improved, but device complexity increases due to additional checking mechanisms
Solution Approach 1:
The patent implements self-service by enabling the DMA controller to autonomously perform error detection without requiring external microprocessor intervention. The DMA independently compares actual error detection codes (computed during data transfers) against pre-stored expected codes, and can autonomously halt operations upon detecting errors. This self-verification mechanism reduces the need for complex external checking systems while maintaining high reliability.
Solution Approach 2:
The patent applies partial action by implementing error detection selectively at transaction control set boundaries rather than continuously monitoring every data bit. The DMA computes error detection codes incrementally during transfers and performs comparisons only at designated check points defined by the transaction control sets. This approach provides sufficient error detection capability while minimizing the complexity overhead of constant monitoring.
3Reliability
If microprocessor manages every DMA data transfer, then reliability is improved, but productivity deteriorates due to microprocessor resource consumption
Solution Approach 1:
The patent implements self-service by enabling the DMA controller to autonomously perform error detection without requiring external microprocessor intervention. The DMA independently compares actual error detection codes (computed during data transfers) against pre-stored expected codes, and can autonomously halt operations upon detecting errors. This self-verification mechanism reduces the need for complex external checking systems while maintaining high reliability.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and storing expected error detection codes in the DMA controller before data transfers occur. These codes are computed based on the transaction control sets and stored in memory, allowing the DMA to autonomously verify data integrity during transfers without microprocessor intervention. This preparatory measure enables the DMA to detect corrupted memory bits independently, resolving the contradiction between autonomous operation and data reliability.
Data Source
AI summary
Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.


