DMA Interconnect Multicast for Coherent Low-Overhead Memory Transfers
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Solution Overview
Problem
Existing System-on-a-Chip (SOC) architectures face inefficiencies in data transfer between memory devices and DMA controllers due to the computational overhead and hardware complexity of using coherent fabrics or chip-level caches, which are slow and costly.
Innovation Solution
Implementing control logic in an on-chip interconnect to facilitate read requests and responses using a broadcast or multicast approach, eliminating the need for snooping logic and chip-level caches by coordinating data transfer among DMA controllers directly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coherent fabrics or chip-level caches are used for data transfer between memory devices and DMA controllers, then data coherence is maintained, but computational overhead and hardware complexity increase
Solution Approach 1:
The patent extracts and removes the coherent fabric and chip-level cache components from the SOC architecture. Instead of using these complex intermediate structures, the invention implements a simplified interconnect that directly coordinates data transfers between memory devices and DMA controllers through basic read/multi-cast operations, eliminating the harmful complexity while preserving memory coherence
Solution Approach 2:
The DMA controllers perform their own coherence management by directly participating in read requests and multi-cast operations through the interconnect. Each DMA controller can independently initiate reads and receive multi-cast responses, eliminating the need for centralized coherence management that would require complex hardware structures
2Reliability
If coherent fabrics or chip-level caches are used for data transfer, then data coherence is maintained, but transfer speed decreases
Solution Approach 1:
By removing the coherent fabric and chip-level cache intermediaries, the patent eliminates the additional processing steps and potential bottlenecks these structures introduce. The direct interconnect approach allows faster data transfer while maintaining coherence through simplified read/multi-cast operations
Solution Approach 2:
The interconnect enables continuous data transfer operations by allowing multiple DMA controllers to simultaneously participate in read requests and receive multi-cast responses. This eliminates the sequential processing delays that would occur with traditional cache-based approaches, maintaining continuous useful action throughout the data transfer process
3Productivity
If traditional interconnect approaches are used, then data transfer is supported, but computational overhead increases
Solution Approach 1:
The DMA controllers autonomously manage their own data transfer operations by directly issuing read requests and receiving multi-cast responses through the interconnect. This self-service approach eliminates the need for complex coherence management logic that would consume additional computational resources and energy
Solution Approach 2:
The interconnect implements multi-cast functionality that efficiently copies data from a single source to multiple destination DMA controllers simultaneously. This copying mechanism reduces computational overhead compared to traditional approaches that would require separate transfer operations or complex cache coherence protocols for each destination
Data Source
AI summary
A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.