DMA Controller Interleaving Scatter Gather Transmissions
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Solution Overview
Problem
In electronic systems, multi-channel analog-to-digital converters face inefficiencies in data transmission due to the lack of direct memory access (DMA) support for interleaving scatter and gather transmissions, leading to CPU occupation and reduced calculating speed when handling large data amounts without DMA, and inefficient data processing without direct memory access.
Innovation Solution
A data storage system comprising a first memory, a second memory, and a memory controller that performs interleaving scatter and gather transmissions by updating addresses and stream numbers using interval and offset values, allowing efficient data transfer between memories without relying solely on the CPU, utilizing a DMA controller with finite state machine capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the central processor unit (CPU) is used to transmit data without a direct memory access (DMA) controller, then data transmission can be performed, but the CPU is occupied for a long period of time, lowering the calculating speed and efficiency
Solution Approach 1:
The patent introduces a DMA controller as an intermediary device between the CPU and memory systems. The DMA controller handles data transmission tasks independently, allowing the CPU to continue executing other instructions without waiting for data transfer operations. This mediator approach resolves the contradiction by enabling data transmission while freeing the CPU from occupation delays.
Solution Approach 2:
The DMA controller is designed to autonomously manage data transmission operations between memory devices without requiring continuous CPU intervention. The controller independently handles address generation, data transfer, and memory access, enabling self-service data transmission that improves productivity while minimizing CPU occupation time.
2Extent of automation
If a direct memory access controller is used, then data transmission automation is improved, but the controller does not support interleaving scatter transmission and interleaving gathering transmission, making it difficult to increase the efficiency of data transmission
Solution Approach 1:
The patent implements segmentation by dividing data transmission into multiple interleaved streams with distinct address patterns. The DMA controller is enhanced to support scatter transmission (dividing data into separate memory locations) and gather transmission (collecting data from separate memory locations). This segmentation capability allows automated transmission of complex multi-channel data while maintaining high efficiency through parallel processing of different data segments.
Solution Approach 2:
The patent introduces dynamic address generation capabilities in the DMA controller, allowing address sequences to change based on transmission mode (scatter or gather). The controller dynamically adjusts addressing patterns, interval values, and stream configurations during operation, enabling flexible automated transmission that adapts to different data formats and memory layouts, thereby improving both automation extent and transmission efficiency.
3Adaptability or versatility
If multi-channel analog-to-digital converter converts data from different sensors repeatedly in turns, then all sensors can be processed, but the data transmission efficiency is reduced due to sequential processing
Solution Approach 1:
The patent implements continuous useful action by enabling the DMA controller to simultaneously manage multiple data streams from different sensors without sequential interruptions. The interleaved scatter/gather transmission modes allow continuous data flow from multiple ADC channels to be transferred to memory in parallel operations, eliminating the repeated turn-based processing and maintaining continuous productive action across all sensor channels.
Data Source
AI summary
A data storage system includes a first memory, a second memory, and a memory controller. The memory controller transmits a first data segment from the first memory to the second memory according to an initial address, adds a first interval value to the initial address to generate a succeeding address, and updates a stream number. When the stream number has not reached a target stream number, the memory controller transmits second data segment from the first memory to the second memory according to the succeeding address, and updates the stream number. When the stream number has reached the target stream number, the memory controller sets the stream number to an initial value, adds an offset value to the initial address to update the succeeding address, and transmits a third data segment from the first memory to the second memory according to the updated succeeding address.