DMA Interrupt Synchronization for Real-Time Control Processors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing control systems face challenges in achieving precise real-time synchronization between processing systems, particularly in avoiding single event upsets and busy waiting issues associated with shared real-time clocks and handshake messages.
Innovation Solution
A system that utilizes a direct memory access controller to trigger interrupts for synchronization messages between processing systems, determining time differences to adjust the synchronization skew of a real-time scheduler, allowing for autonomous message transfer and task execution without processor intervention, thereby maintaining synchronization and optimizing execution frame times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a shared real-time clock is used for synchronization, then close synchronization is achieved, but the system risks single event upsets affecting multiple systems and requires dedicated signal paths
Solution Approach 1:
The patent divides the synchronization function into separate segments: each processing system maintains its own independent real-time clock rather than sharing a single clock. This segmentation isolates potential failures to individual systems while maintaining synchronization through message exchange, resolving the contradiction between precision and reliability.
Solution Approach 2:
The patent introduces synchronization messages as an intermediary mechanism between processing systems. These messages carry timestamp information that allows systems to calculate and adjust their synchronization skew without direct clock sharing, achieving precise synchronization while maintaining system independence and reliability.
2Measurement precision
If handshake and acknowledgement messages are exchanged between processing systems, then synchronization is achieved, but busy waiting occurs as systems continually poll receiver registers
Solution Approach 1:
The patent implements periodic synchronization messages sent at defined intervals rather than continuous polling. The real-time stamps in these periodic messages allow receiving systems to calculate synchronization skew without continuously checking receiver registers, eliminating busy waiting while maintaining precision.
Solution Approach 2:
The patent uses feedback mechanisms where receiving systems calculate synchronization skew based on timestamp differences and adjust their local clocks accordingly. This feedback loop achieves precise synchronization without requiring continuous polling, reducing time loss while maintaining accuracy.
3Reliability
If processing systems continually poll receiver registers while waiting for responses, then synchronization is maintained, but system efficiency decreases due to busy waiting
Solution Approach 1:
The patent implements preliminary action by having transmitting systems send synchronization messages with timestamps in advance, rather than requiring receiving systems to continuously poll for responses. This allows receiving systems to process messages asynchronously, maintaining reliability while improving productivity by eliminating busy waiting.
Data Source
AI summary
A system includes a memory system and a processor of a first processing system including a processor core, a direct memory access controller, and a communication interface. The processor core is configured to execute a plurality of instructions to configure the direct memory access controller to trigger a transmitter interrupt upon transmitting a first synchronization message through the communication interface to a second processing system, configure the direct memory access controller to trigger a receiver interrupt upon receiving a second synchronization message from the second processing system, determine a time difference between triggering of the transmitter interrupt and the receiver interrupt, and adjust a synchronization skew of a real-time scheduler based on the time difference to tune real-time synchronization between the first processing system and the second processing system.