DMA Latency Estimation for TSN Frame Scheduling
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Solution Overview
Problem
In time sensitive networks (TSN), determining the worst case frame retrieval time due to varying DMA latency is challenging, leading to increased frame buffering and transmission latency.
Innovation Solution
The proposed solution involves determining an advance time offset based on an estimated frame retrieval time, which is calculated using an estimated DMA latency. This estimated DMA latency is obtained by measuring and averaging DMA latency over a window of time, allowing for dynamic adjustments to account for changes in DMA load and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If worst case frame retrieval time is used to set advance time offset, then frame transmission reliability is improved, but frame transmission latency increases
Solution Approach 1:
The patent applies dynamics by transitioning from a static worst-case DMA latency value to a dynamic estimated DMA latency that adapts to changing system conditions. The scheduling circuit continuously monitors actual DMA latency measurements and updates the estimated value, allowing the advance time offset to dynamically adjust based on real-time system performance rather than relying on conservative fixed worst-case assumptions.
Solution Approach 2:
The patent implements feedback by having the scheduling circuit measure actual DMA latency for each frame retrieval operation and use these measurements to update the estimated DMA latency. This closed-loop feedback mechanism allows the system to learn from actual performance and continuously optimize the advance time offset, balancing reliability and latency based on observed system behavior rather than static worst-case predictions.
2Reliability
If worst case frame retrieval time is used, then frame scheduling reliability is improved, but number of frames waiting in buffer increases
Solution Approach 1:
The patent applies dynamics by replacing the static worst-case frame retrieval time with a dynamic estimated frame retrieval time that reflects actual system conditions. The scheduling circuit continuously updates this estimate based on measured DMA latency, allowing the buffer management to adapt to changing system performance and reduce unnecessary frame accumulation when conditions are favorable.
Solution Approach 2:
The patent implements feedback by measuring actual frame retrieval times and using these measurements to update the estimated frame retrieval time. This feedback loop enables the scheduling circuit to adjust buffer management strategies based on real performance data, reducing the number of frames waiting in buffer when actual retrieval times are better than worst-case predictions while maintaining scheduling reliability.
3Measurement precision
If DMA latency measurements are taken over a window of time and averaged, then estimation accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent applies partial action by using a moving window of limited size (e.g., 8 measurements) rather than analyzing all historical data. This selective sampling provides sufficient estimation accuracy for practical purposes while significantly reducing computational complexity compared to analyzing complete historical datasets or using complex statistical models.
Solution Approach 2:
The patent changes the parameter of data aggregation by using a simple average of recent measurements rather than complex weighted algorithms or long-term statistical analysis. This parameter change maintains measurement precision adequate for TSN requirements while dramatically simplifying the computational burden on the scheduling circuit.
Data Source
AI summary
A network station scheduling a frame to be transmitted by a transmitter of the network station at a transmit time. The transmit time is based on a first clock. A request is then issued to a direct memory access (DMA) circuit to retrieve the frame from a system memory. An advance time offset associated with the first clock is determined based on an estimated DMA latency of the DMA circuit. A frame retrieved by the DMA circuit is provided to a staging circuit. When a time of a second clock reaches the transmit time of the frame in the staging circuit, the frame is transmitted at the transmit time. In an example, a time of the first clock is ahead of a time of the second clock by the advance time offset.