DMA and LSU Data Transposition for Faster Column Memory Access

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Solution Overview

Problem

Existing computer systems face inefficiencies in accessing memory banks as columns require multiple operations, while rows can be accessed in a single operation, necessitating a transposition of data to optimize memory access.

Innovation Solution

A computer system architecture that utilizes a DMA controller and load-store hardware to perform XOR and swap operations to transpose data from main memory into processor registers, reducing the number of instruction cycles required for transposition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If data is accessed as columns in memory banks, then data can be retrieved in a structured manner, but multiple memory operations are required increasing access time

Engineering Contradiction:

Improvedata access structureVSAvoidmemory access time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The system performs preliminary transposition of data rows into column-major order in the processor registers before actual processing begins. This preliminary reorganization allows subsequent column access operations to proceed efficiently without requiring multiple sequential memory operations, thereby resolving the time loss associated with columnar data access patterns.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The memory access operation is segmented into two distinct phases: (1) a transposition phase that reorganizes data in processor registers, and (2) an efficient column access phase that retrieves pre-organized data. This segmentation allows the system to optimize each phase independently, with the transposition phase preparing data structures that eliminate the need for multiple sequential memory operations during the access phase.

Inventive Principle:

Principle #1Segmentation

2Productivity

If hardware transposition capability is added to speed up memory access, then processing time is reduced, but device complexity increases

Engineering Contradiction:

Improvememory access speedVSAvoidhardware complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The load-store unit is designed with multi-functionality, serving both as a standard data loading device and as a transposition hardware accelerator. By integrating the transposition capability into the existing load-store unit, the system achieves hardware transposition without adding separate dedicated transposition hardware, thus improving memory access speed while minimizing the increase in overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The transposition function is merged with the load-store unit, combining multiple functions (data loading and data transposition) into a single hardware component. This merging approach allows the system to perform hardware-based transposition operations without requiring additional separate hardware modules, thereby achieving improved memory access performance with minimal impact on hardware complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12613699B2DMA controller and LSU to transpose data arrays stored in main memory for storage in processor registers

Publication Date: 2026.04.28 SONY INTERACTIVE ENTERTAINMENT LLC

AI summary

One or more hardware elements operate on an array of data from a memory to generate a shuffled array of data. A subsequent of hardware operations on the shuffled array of data produces a transposed array of data in which rows and columns of the array of data are transposed. A load-store unit may then load the array of transposed data into a plurality of processor registers.