User Level DMA Memory Access Control via Logical Address Translation
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Solution Overview
Problem
Current memory access control systems in high-definition image processing systems face performance instability due to unauthorized access by processing units, particularly when I/O devices directly designate physical addresses, leading to potential errors in device drivers that can severely impact system efficiency and stability.
Innovation Solution
A memory access control system that includes an I/O access control apparatus and a process control apparatus, which translates logical addresses into physical addresses within a DMA address space, allowing user processes to directly access the DMA address space while ensuring access permissions are granted only to authorized DMA requestors through an IOID-based mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If I/O devices directly designate physical addresses for memory access, then processing speed is improved, but system stability deteriorates due to unauthorized access and programming errors
Solution Approach 1:
The patent introduces an I/O access control apparatus as an intermediary between I/O devices and the DMA address space. This mediator translates logical addresses to physical addresses and controls access permissions, allowing fast direct memory access while preventing unauthorized access through the address translation and permission checking mechanisms
Solution Approach 2:
The patent segments the address space by introducing a logical address space separate from the physical DMA address space. The I/O access control apparatus manages this segmentation through address translation, allowing different permission levels and access controls for different address regions while maintaining efficient physical access
2Reliability
If user processes directly access DMA address space through device drivers, then access control is improved, but processing efficiency deteriorates due to device driver overhead
Solution Approach 1:
The patent enables user processes to perform DMA transfers independently by providing them with logical addresses that they can use to directly access the DMA address space. The I/O access control apparatus handles the address translation and permission verification, allowing user processes to self-manage DMA operations without device driver intervention, thus improving efficiency while maintaining access control
3Reliability
If device drivers manage all DMA transfers, then access control is ensured, but system overhead increases and processing efficiency decreases
Solution Approach 1:
The patent extracts the address translation and permission checking functions from the device drivers and places them in the I/O access control apparatus. This separation allows device drivers to focus on high-level DMA management while the access control apparatus handles low-level address translation and permission verification, reducing device driver complexity and overhead
Data Source
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AI summary
A memory access control apparatus (300) receives from a DMA requestor (336) an access request command, which contains an IOID, for a DMA address space that is a memory area used for a DMA transfer, and determines whether the access is permitted or not and executes the access if it is permitted. The operating system on the PU (112) sets in MMU (334) the correspondence relationship between the logical address space of a user process and the DMA address space. When the user process instructs to access the DMA address space by specifying a logical address, the MMU (334) translates the logical address into a physical address of the DMA address space.