DMA Memory Command Processing to Reduce Host-Core Bandwidth Occupancy
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Solution Overview
Problem
Conventional data processing methods experience performance degradation due to continuous occupancy of the host core's data bandwidth and inevitable barrier overheads when transferring data between static random access memory (SRAM) and dynamic random access memory (DRAM), particularly in out-of-order memory command devices.
Innovation Solution
A data processing apparatus and method that utilizes a host core to generate a control message, a direct memory access (DMA) to create a memory request, and a memory controller to convert this request into commands for a dynamic random access memory (DRAM), allowing in-order operations and reducing host core bandwidth occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the host core directly generates memory commands for PIM operations, then the processing can be performed, but the host core's data bandwidth is continuously occupied causing performance degradation
Solution Approach 1:
The patent extracts the memory command generation function from the host core and assigns it to a dedicated DMA controller. The host core generates only control messages, while the DMA controller independently generates memory commands based on these messages, thereby releasing the host core's data bandwidth for other processing tasks and eliminating continuous occupancy.
Solution Approach 2:
The patent introduces a DMA controller as an intermediary component between the host core and the memory system. This mediator translates high-level control messages from the host core into detailed memory commands, handling the complexity of memory management without burdening the host core and enabling parallel operation of multiple processing tasks.
2Productivity
If the host core operates out-of-order to improve performance, then processing efficiency increases, but barrier overhead is inevitable to control in-order PIM devices
Solution Approach 1:
The DMA controller serves as an intermediary that bridges the out-of-order execution of the host core and the in-order requirements of PIM devices. It receives out-of-order control messages from the host core, internally manages the ordering and synchronization using barrier mechanisms, and generates properly ordered memory commands, thereby isolating the complexity of barrier management from the host core.
Solution Approach 2:
The patent extracts the barrier management and command ordering complexity from the host core and concentrates it in the DMA controller. This allows the host core to maintain high out-of-order execution efficiency while the DMA controller handles the necessary synchronization and ordering overhead independently.
3Quantity of substance
If data is transferred between SRAM and DRAM using conventional methods, then the transfer can be performed, but performance degradation occurs due to host core bandwidth occupancy
Solution Approach 1:
The patent extracts the data transfer control function from the host core and assigns it to the DMA controller. The host core generates control messages for data transfer operations, while the DMA controller independently manages the actual data movement between SRAM and DRAM, enabling parallel execution of transfer operations without occupying host core bandwidth and thus maintaining high overall system performance.
Data Source
AI summary
A data processing apparatus and method are disclosed. The data processing apparatus may include a host core configured to generate a control message to control a direct memory access (DMA), the DMA configured to generate a memory request based on the control message, a memory controller configured to generate a memory command based on the memory request, and a processor configured to perform an operation in a memory based on the memory command.