IC Memory Monitoring via DMA for Real-Time Debugging
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Solution Overview
Problem
Current debugging methods for microcontrollers/microprocessors require extensive use of chip simulation systems and breakpoints, which can be time-consuming and inefficient for monitoring the execution status of programs.
Innovation Solution
A monitoring system for integrated circuits (ICs) that includes input and output pins, a controller, a timer, a memory, and a direct memory access (DMA) device, allowing for real-time data transmission from the IC to an external module using a bridge, enabling simultaneous debugging and monitoring of memory contents without processor intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip simulation system and breakpoints are used to monitor program execution status, then debugging capability is improved, but development time and debugging time are increased
Solution Approach 1:
The patent extracts the monitoring function from the processor's normal execution flow by implementing a dedicated monitoring mode that independently accesses memory contents through DMA technology. This allows program status monitoring to be separated from the main program execution, enabling simultaneous debugging without interrupting or slowing down the development process.
Solution Approach 2:
The patent implements preliminary action by pre-configuring the monitoring system with DMA channels and memory mapping before actual debugging begins. The bridge device is pre-established to connect the processor to external debugging equipment, allowing immediate monitoring capability without setting up breakpoints or simulation environments during the debugging process.
2Productivity
If processor is used to transfer data from memory, then data transfer is achieved, but processor workload is increased
Solution Approach 1:
The patent introduces DMA (Direct Memory Access) controller as an intermediary device between memory and external devices. The DMA controller independently handles data transfer operations without requiring processor intervention, thus achieving efficient data transfer while keeping the processor workload minimal. The processor only needs to initiate and control the DMA transfer, not execute each data movement operation.
Data Source
AI summary
An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.