DMA Memory Noise Detection for Power-Noise Reliability

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Solution Overview

Problem

Memory systems experience errors due to power noise during data transmission, which existing technologies fail to adequately detect and correct, leading to inefficiencies and reduced reliability.

Innovation Solution

A memory device with a control logic that generates noise detection data to identify power noise during direct memory access (DMA) operations, allowing a memory controller to re-perform the DMA operation when noise is detected, thereby improving reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If noise detection is implemented during DMA operations, then data reliability is improved, but device complexity increases

Engineering Contradiction:

Improvedata reliabilityVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The memory device performs self-diagnosis by detecting power noise during DMA operations and generating noise detection data autonomously, eliminating the need for external monitoring hardware and reducing overall system complexity while improving reliability

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The noise detection data is fed back to the memory controller, which uses this information to determine whether to re-perform DMA operations, creating a closed-loop system that improves data reliability through automatic error correction without adding complex external control mechanisms

Inventive Principle:

Principle #23Feedback

2Reliability

If DMA operations are re-performed when noise is detected, then data accuracy is improved, but loss of time increases

Engineering Contradiction:

Improvedata accuracyVSAvoidoperation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Instead of re-performing all memory operations, only the specific DMA operations that were affected by power noise are re-executed based on the noise detection data, minimizing time loss while ensuring data accuracy for affected operations

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

Power noise is detected during the DMA operation itself rather than after completion, allowing for immediate identification of affected operations and enabling selective re-performance only when necessary, thus reducing overall time loss

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250390229A1Memory device, memory controller, and operating method of memory system including the memory device and the memory controller

Publication Date: 2025.12.25 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device includes a memory cell array including a plurality of memory cells, and with respect to the memory cell array, a control logic configured to control a memory operation corresponding to a command and an address provided from a memory controller outside the memory device, wherein the control logic is configured to, during a direct memory access (DMA) operation of transmitting operation data corresponding to the command and the address, generate noise detection data by detecting whether noise occurred in power provided to the memory device, and transfer the noise detection data to the memory controller.