Direct Memory Access Controller Multi-Destination Transfer
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Solution Overview
Problem
Conventional methods for multi-destination direct memory access transfers in video processing and graphics applications suffer from high bandwidth costs, bottlenecks, congestion, and synchronization issues, particularly when creating multiple copies of frames in memory, which limits system performance and increases internal memory bandwidth.
Innovation Solution
A direct memory access controller that reads data from an external memory, processes it, and writes it to multiple destinations within an internal memory, allowing for decimation, interpolation, filtering, and parallel transfers to reduce bandwidth utilization and avoid congestion, while maintaining efficient data storage and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two independent transfers are used to create multi-destination copies, then the frame can be read from source memory to multiple locations, but the bandwidth cost of the source memory becomes high and the total transfer is slow
Solution Approach 1:
The patent combines multiple independent transfers into a single DMA operation that reads from the source memory location once and writes to multiple destination locations simultaneously. This merging approach reduces the total bandwidth consumption from two separate frame reads to one frame read while maintaining the ability to create multiple copies at different destinations.
Solution Approach 2:
The patent segments the data transfer process into a single read operation followed by multiple write operations to different destinations. The DMA controller is configured to perform one read from the source and distribute the data to multiple destinations within a single transfer operation, optimizing bandwidth utilization.
2Quantity of substance
If sequential transfers are used to create multi-destination copies, then bandwidth consumption is reduced, but congestion is created in the destination memory and synchronization issues occur
Solution Approach 1:
The patent merges multiple sequential transfer operations into a single DMA operation that performs both read and write operations atomically. This ensures that the destination memory locations are updated simultaneously without creating congestion or synchronization issues that would occur with sequential transfers.
Solution Approach 2:
The DMA controller acts as an intermediary that coordinates the data transfer from source memory to multiple destination locations. It manages the transfer operations to ensure proper synchronization and avoid congestion in the destination memory, eliminating the need for complex coordination between multiple sequential transfers.
3Adaptability or versatility
If multiple copies of frames are created in memory, then video processing and graphics applications can access data at different locations, but the internal memory bandwidth is increased
Solution Approach 1:
The patent merges multiple write operations to different destination locations into a single DMA transfer operation. This allows the system to create multiple copies of frame data at different memory locations without increasing the internal memory bandwidth consumption, as all writes occur within the context of a single coordinated transfer.
Data Source
AI summary
An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location.