DMA-Based Multi-Processor Array Architecture
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Solution Overview
Problem
Existing multi-processor array architectures face performance degradation due to bandwidth sharing and arbitration-induced losses in bus-based systems, and scalability limitations in Network-on-Chip architectures, along with inefficiencies in synthesizing and mapping hardware description languages to resource-efficient structures.
Innovation Solution
A direct memory access (DMA)-based multi-processor array architecture is implemented in a single integrated circuit, utilizing topologically coupled processing units with dual-ported random access memory and decoders, which eliminates the need for complex arbitration and allows random access to memory, thereby improving performance and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If bus-based communication is used in multi-processor array, then ease of operation is improved, but productivity deteriorates due to bandwidth sharing and arbitration-induced losses
Solution Approach 1:
The patent extracts the arbitration mechanism from the system by implementing direct point-to-point connections between processors and memory via DMA channels, eliminating the need for shared bus arbitration and thereby removing the source of productivity degradation while preserving ease of operation
Solution Approach 2:
The patent segments the communication infrastructure into dedicated DMA channels for each processor, allowing independent data transfer paths that avoid bandwidth sharing conflicts. This segmentation enables simultaneous data transfers without arbitration overhead, improving productivity while maintaining operational simplicity
2Productivity
If Network-on-Chip architecture is used in multi-processor array, then productivity is improved, but device complexity worsens due to distributed arbitration and routing mechanisms
Solution Approach 1:
The patent removes the complex distributed arbitration and routing mechanisms of NoC architectures by implementing direct wired connections between processors and memory through DMA blocks. This extraction eliminates the need for sophisticated network protocols and arbitration logic, reducing device complexity while maintaining high productivity through dedicated communication paths
3Device complexity
If FIFO-based streaming data approach is used, then device complexity is reduced, but productivity deteriorates due to constrained random access capability
Solution Approach 1:
The patent introduces DMA blocks as intermediary components that provide random access memory interfaces between processors and memory resources. These DMA intermediaries enable efficient random access operations without requiring complex memory management logic in the processors themselves, thereby improving productivity while keeping device complexity manageable
Solution Approach 2:
The patent extracts the random access capability from the FIFO streaming interface by implementing separate DMA-based memory access paths. This allows processors to perform random access operations independently of the streaming data flow, improving productivity for applications requiring random access while maintaining the simplicity of FIFO-based streaming for sequential data
Data Source
AI summary
A direct memory access (“DMA”)-based multi-processor array architecture that may be implemented in a single integrated circuit is described. The integrated circuit includes a plurality of processing units. A first processing unit and a second processing unit of the plurality of processing units are topologically coupled via a first DMA block. The first DMA block includes a first dual-ported random access memory and a first decoder. A multiple-processor array is provided by topologically coupling the first processing unit and the second processing unit via the first direct memory access block.