DMA Engine Network Offload for Remote Memory Access Latency

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Solution Overview

Problem

Disaggregated memory architectures in data centers experience increased latency due to remote memory access through network elements, which affects computing efficiency and resource utilization.

Innovation Solution

Implement a data center architecture with chassis-less sleds containing specific resource types, such as compute, memory, and storage, connected via high-speed interconnects and optical fabrics, allowing independent resource upgrades and optimized allocation for workload execution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory pools are located remote from compute nodes to enable disaggregated memory architecture, then memory capacity and resource utilization are improved, but access latency increases due to network traversal

Engineering Contradiction:
Improvememory capacityVSAvoidaccess latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The system segments memory resources from compute nodes, creating independent memory pools that can be dynamically allocated. Memory pools are divided into multiple memory devices that can be independently managed and accessed, allowing flexible resource allocation while maintaining physical separation for scalability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A fabric interconnect acts as an intermediary between compute nodes and remote memory pools, enabling efficient data transmission. The fabric provides standardized communication protocols and routing capabilities that optimize network traversal and reduce access latency despite the physical distance between components.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If traditional packet formation and processing is used for remote memory access, then network communication flexibility is maintained, but access latency increases due to additional processing overhead

Engineering Contradiction:
Improvenetwork communication flexibilityVSAvoidprocessing overhead
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-establishing communication channels and buffering data packets before actual memory access operations. Data is pre-processed and staged in buffers closer to the memory pools, reducing the need for repeated packet formation and processing during actual access operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The communication protocol dynamically adapts between packet-based and direct memory access modes based on workload characteristics. For sequential access patterns, the system uses optimized direct access paths, while for random access patterns, it falls back to flexible packet processing, thereby reducing processing overhead while maintaining versatility.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250385808A1Direct memory access (DMA) engine with network interface capabilities
Publication Date: 2025.12.18 INTEL CORP
  • US20250385808A1 patent drawing
  • US20250385808A1 patent drawing
  • US20250385808A1 patent drawing

AI summary

Examples described herein include one or more processors; a network interface; and a direct memory access (DMA) engine communicatively coupled to the one or more processors. In some examples, the DMA engine is to receive a DMA data access request and based on an address in the DMA data access request corresponding to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device. In some examples, the DMA data access request includes a source address, a destination address, and a length. In some examples, if the source address corresponds to a local memory device and the destination address corresponds to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device, wherein the at least one packet includes data stored at the source address.