DMA Engine Non-Sequential Addressing for Matrix Transposition

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Solution Overview

Problem

Existing direct memory access (DMA) technologies are limited to sequential read and write patterns, which can be inefficient for certain data processing tasks such as matrix transposition and interleaving of wireless data, as they require sequential memory addressing.

Innovation Solution

The implementation of a system-on-a-chip (SoC) with a DMA engine that can perform non-sequential read and write operations using different patterns, allowing data to be written or read from non-sequential memory addresses, enabling tasks like matrix transposition and interleaving without the need for sequential addressing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If sequential memory addressing is used for DMA operations, then the DMA engine can perform simple and reliable data transfer, but it cannot efficiently handle non-sequential data access patterns such as matrix transposition and interleaving

Engineering Contradiction:

Improvedata access pattern flexibilityVSAvoidDMA engine complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The DMA engine implements dynamic address generation by switching between sequential and non-sequential addressing modes based on operation requirements. The address generator is configured to support multiple addressing patterns including sequential, interleaved, and transposed addressing, allowing the system to adapt to different data access needs without requiring multiple dedicated DMA engines.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the addressing parameters of the DMA engine to support non-sequential access patterns. By modifying the address generation logic to accept configurable parameters for stride, interleaving factor, and transposition dimensions, the DMA engine can efficiently handle matrix transposition and data interleaving operations while maintaining a single unified architecture.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If sequential memory access is used, then the memory addressing logic remains simple, but data processing tasks like matrix transposition require additional processing steps and time

Engineering Contradiction:

Improvedata processing efficiencyVSAvoidprocessing time for non-sequential operations

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The DMA engine performs preliminary addressing calculations by pre-configuring non-sequential access patterns for operations like matrix transposition and interleaving. The address generator computes the complete address sequence in advance based on the specified pattern, eliminating the need for runtime address calculations and reducing processing time for these operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an address generator as an intermediary component between the DMA controller and memory. This address generator translates high-level operation descriptions (such as matrix transposition parameters) into specific memory addresses, enabling efficient non-sequential access without requiring complex control logic in the main processor or additional processing steps.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Adaptability or versatility

If the DMA engine only supports sequential addressing, then the addressing logic is simple and fast, but it cannot perform operations like matrix transposition and data interleaving efficiently

Engineering Contradiction:

Improvesupport for multiple addressing patternsVSAvoidaddress generation logic complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The DMA engine is designed with universal addressing capabilities that can handle sequential, non-sequential, interleaved, and transposed addressing patterns through a single unified architecture. The address generator accepts configurable parameters that define the desired access pattern, allowing the same hardware to efficiently perform diverse operations such as data transfer, matrix transposition, and interleaving without requiring multiple specialized engines.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11669464B1Multi-addressing mode for DMA and non-sequential read and write patterns

Publication Date: 2023.06.06 XILINX INC

AI summary

Examples herein describe performing non-sequential DMA read and writes. Rather than storing data sequentially, a DMA engine can write data into memory using non-sequential memory addresses. A data processing engine (DPE) controller can submit a first job using first parameters that instruct the DMA engine to store data using a first non-sequential write pattern. The DPE controller can also submit a second job using second parameters that instruct the DMA engine to store data using a second, different non-sequential write pattern. In this manner, the DMA engine can switch to performing DMA writes using different non-sequential patterns. Similarly, the DMA engine can use non-sequential reads to retrieve data from memory. When performing a first DMA read, the DMA engine can retrieve data from memory using a first sequential pattern and then perform a second DMA read where data is retrieved from memory using a second non-sequential read pattern.