DMA Controller Offload Filter for Network Packet Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional network interface devices struggle with high data rates and power efficiency when handling complex network data structures, as CPUs are not ideally suited for such tasks, leading to a need for enhanced network processing circuitry to assist with network processing tasks.
Innovation Solution
The integration of an offload filter within a DMA controller that supports network packet processing, including classification, routing, and checking, allowing the DMA controller to perform network packet processing concurrently with data transfer, and a scheduling mechanism to manage DMA transfer conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple network interface device is used with complex software on CPU, then device complexity is reduced, but processing speed and power efficiency deteriorate at high data rates
Solution Approach 1:
The patent extracts network processing functions from the CPU and implements them directly in the DMA controller hardware. The DMA controller includes dedicated circuitry for packet classification, routing decisions, and checksum validation, removing these tasks from software execution and placing them in hardware for parallel processing during data transfer.
Solution Approach 2:
The patent merges network processing functionality with the DMA controller by integrating packet processing units, classification tables, and routing logic directly into the DMA controller architecture. This combination allows network processing and data transfer to occur simultaneously without requiring separate CPU intervention.
2Device complexity
If a simple network interface device is used with complex software on CPU, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The patent extracts power-intensive network processing tasks from the CPU and relocates them to dedicated hardware circuits within the DMA controller. Hardware-based packet classification and routing decisions consume significantly less power than software execution, especially at high data rates where CPU processing would be continuously required.
Solution Approach 2:
The DMA controller performs network processing functions autonomously during data transfer without requiring CPU involvement. The integrated classification and routing circuits automatically make decisions based on packet headers and destination addresses, enabling self-service processing that reduces overall system power consumption.
3Productivity
If DMA controller is used for data transfer, then CPU efficiency is improved, but network processing capability is insufficient
Solution Approach 1:
The patent enhances the DMA controller with multi-functional capabilities including packet classification, routing decisions, checksum validation, and data transfer. This universal design allows the same hardware component to perform both traditional DMA data transfer functions and network protocol processing, eliminating the need for separate specialized hardware.
Solution Approach 2:
The patent combines traditional DMA data transfer functions with network processing capabilities in a single integrated controller. The merged architecture includes shared memory spaces, unified control logic, and coordinated data paths that allow seamless operation of both data transfer and packet processing functions.
4Productivity
If network packet processing is performed during DMA transfer, then system performance is improved, but device complexity increases
Solution Approach 1:
The patent segments the DMA controller into functional modules including packet classification units, routing decision circuits, checksum validation blocks, and data transfer engines. Each module operates independently with dedicated resources, allowing network processing to be performed during data transfer while maintaining modular architecture that manages complexity through functional decomposition.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is passed through a transmission filter for processing. This processing may include the addition or removal of transmission protocol headers and footers, and determination of the destination of the data. This processing may also include hash-based packet classification and checksum generation and checking. Upon completion of the processing, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device.