DMA Page Request Interface for Cached Host Address Translation

Solution Overview

Problem

The continual need for address translations in memory systems, particularly in systems with multiple non-volatile memory express (NVMe) devices, creates bottlenecks in performance, speed, latency, and quality-of-service due to the overhead of translating virtual to physical addresses across PCIe buses, leading to increased I/O traffic and inefficiencies.

Innovation Solution

Implementing an address translation cache (ATC) within the host interface circuitry to store address translations for future access, and incorporating a page request interface (PRI) handler to automate page miss requests, reducing the need for pinning large amounts of host memory and minimizing cache misses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If address translations are performed frequently for host memory access, then memory sub-system can handle more submission and completion queues, but I/O traffic over PCIe buses increases and performance slows

Engineering Contradiction:

Improvehandling capacity of submission and completion queuesVSAvoidmemory command speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent implements an address translation cache that creates a copy of the address translation table within the memory sub-system. This cache stores translated addresses locally, allowing the system to handle multiple submission and completion queues without repeatedly accessing the host memory for translations, thereby reducing I/O traffic and maintaining command speed.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The system performs address translations in advance by pre-loading translation entries into the cache before they are actually needed for memory operations. This preliminary action allows subsequent memory commands to execute faster without waiting for real-time translations from the host, resolving the contradiction between handling queue capacity and command speed.

Inventive Principle:

Principle #10Preliminary action

2Ease of operation

If the translation agent handles all address translations, then host memory access is simplified, but I/O traffic increases and latency increases

Engineering Contradiction:

Improvehost memory access simplicityVSAvoidaddress translation latency

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

The address translation cache acts as an intermediary between the host memory and the memory sub-system. It absorbs the complexity of address translation by maintaining a local copy of translation tables, allowing the host memory access to remain simple while reducing translation latency through local cache hits.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs address translations in advance by pre-loading translation entries into the cache before they are actually needed for memory operations. This preliminary action allows subsequent memory commands to execute faster without waiting for real-time translations from the host, resolving the contradiction between handling queue capacity and command speed.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If large amounts of host memory are pinned for DMA operations, then DMA operations can proceed without page faults, but memory resource consumption increases

Engineering Contradiction:

ImproveDMA operation reliabilityVSAvoidhost memory pinned

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The system performs address translations in advance by pre-loading translation entries into the cache before they are actually needed for memory operations. This preliminary action allows subsequent memory commands to execute faster without waiting for real-time translations from the host, resolving the contradiction between handling queue capacity and command speed.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements an address translation cache that creates a copy of the address translation table within the memory sub-system. This cache stores translated addresses locally, allowing the system to handle multiple submission and completion queues without repeatedly accessing the host memory for translations, thereby reducing I/O traffic and maintaining command speed.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS12632391B2Page request interface support in handling direct memory access with caching host memory address translation data

Publication Date: 2026.05.19 MICRON TECHNOLOGY INC

AI summary

A method includes buffering, in a descriptor queue, descriptors associated with translation units of an LBA-based, direct memory access (DMA) read command of a host system, each descriptor to be linked with a pointer including a physical destination for data associated with a respective translation unit. The method includes sending address translation requests to an address translation circuit for the pointers of respective translation units and detecting an address translation request miss at a cache of the address translation circuit for a first pointer of a first translation unit linked to a first descriptor of the plurality of descriptors. The method includes causing a translation miss message to be sent to a page request interface (PRI) handler, the translation miss message containing a virtual address of the first pointer and to trigger the PRI handler to send a page miss request to a translation agent of the host system.