Direct Memory Access Architecture Parallel Read Write Channels
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Solution Overview
Problem
The current chain DMA technology has low transfer efficiency due to limitations such as lack of support for out-of-order data reception, inability to interconnect with standard buses, and inability to perform read and write processing in parallel.
Innovation Solution
A direct memory access architecture is introduced, comprising a direct memory access control component, a read data moving component, a write data moving component, and a data storage component. This architecture includes a control register, read and write descriptor storage components, and command transfer components to manage and execute read and write commands efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chain DMA is used to transfer data between non-contiguous memory addresses, then data transfer can be completed without CPU intervention, but transfer efficiency remains low due to sequential processing requirements
Solution Approach 1:
The patent segments the DMA transfer process into multiple independent channels (read channel and write channel), each capable of handling different memory segments simultaneously. The descriptor ring is divided into multiple descriptor structures that can be processed in parallel by different channels, resolving the contradiction by enabling concurrent processing without requiring a single complex sequential controller.
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing multiple DMA channels that can operate simultaneously. Instead of processing descriptors sequentially in a single dimension, the system processes multiple descriptor rings across multiple channels in parallel, fundamentally changing the processing dimension and achieving high efficiency without increasing individual channel complexity.
2Productivity
If traditional DMA architecture is used, then data transfer can be performed, but read and write operations cannot be performed in parallel
Solution Approach 1:
The patent merges multiple DMA functionalities into a unified architecture that supports both read and write operations through separate channels. The read DMA channel and write DMA channel are combined in a way that allows simultaneous operation, with each channel having its own descriptor ring but sharing common resources like the data bus when needed, achieving parallel processing without duplicating entire DMA subsystems.
Solution Approach 2:
The patent implements a universal DMA architecture where the same hardware infrastructure supports multiple functions including read operations, write operations, and different data transfer modes. The descriptor ring structure and control logic are designed to be multi-functional, allowing the system to perform various DMA operations through a single unified interface rather than requiring separate dedicated hardware for each function.
3Productivity
If interrupt is triggered after each physically contiguous data transfer in block DMA, then data transfer can be completed, but CPU resources are frequently occupied
Solution Approach 1:
The patent implements preliminary action by pre-configuring descriptor rings with multiple descriptor entries that define the entire data transfer sequence in advance. The DMA controller loads the complete descriptor ring into memory before transfer begins, allowing it to process multiple descriptors sequentially without CPU intervention. The CPU only needs to initiate the transfer and handle completion interrupts, rather than being involved in each intermediate step.
Solution Approach 2:
The patent ensures continuity of useful action by implementing a descriptor ring structure that allows the DMA controller to continuously process descriptors without CPU intervention. The circular buffer mechanism enables the controller to wrap around from the end of the descriptor ring back to the beginning, maintaining continuous data transfer operation. This eliminates idle periods and ensures the DMA controller is always performing useful data transfer work.
4Loss of time
If linked list is used to describe non-contiguous memory space in chain DMA, then interrupt generation is reduced, but transfer efficiency remains low
Solution Approach 1:
The patent replaces the mechanical linked list structure with a memory-resident descriptor ring architecture. Instead of using pointer-based linked lists that require sequential traversal and memory access, the descriptor ring is stored in contiguous memory with direct address calculations. This substitution eliminates the overhead of linked list traversal and enables more efficient descriptor processing while maintaining the ability to handle non-contiguous memory spaces.
Data Source
AI summary
Provided is a direct memory access architecture, including: a direct memory access control component, a read data moving component, a write data moving component and a data storage component; wherein the direct memory access control component includes a control register, a read descriptor storage component, a write descriptor storage component, a read command transfer component and a write command transfer component; the control register is configured to obtain descriptor address information; the read descriptor storage component is configured to store a read descriptor obtained by using the control register; the write descriptor storage component is configured to store a write descriptor obtained by using the control register; the read command transfer component is configured to send, to the read data moving component, a read command; the write command transfer component is configured to send, to the write data moving component, a write command.