DMA Parity Offload in Storage Arrays for Processor Throughput

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Solution Overview

Problem

Existing systems that compute parity information in storage arrays utilize system processors, leading to processing overhead and delays in critical system operations.

Innovation Solution

A system and method that offloads parity calculation from the system processor by using a DMA controller to transfer data between processor and accelerator memories, where the accelerator performs the parity calculation and writes the results to storage array drives.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the system processor is used to compute parity information, then the parity calculation can be performed, but system processor resources are consumed and critical system operations are delayed

Engineering Contradiction:

Improvedata protectionVSAvoidsystem processor throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the parity calculation function from the system processor and implements it in dedicated hardware logic within the storage array controller. This separation allows the system processor to focus on critical operations while the hardware logic handles parity computations independently and in parallel, resolving the contradiction between data protection requirements and processor productivity.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a dedicated parity calculation unit as an intermediary component between the system processor and the storage array. This intermediary handles the computationally intensive parity operations, preventing the system processor from being bottlenecked by these calculations while ensuring data protection through accurate parity generation.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the system processor is used for parity calculation, then parity information can be generated, but processing overhead increases and delays occur in critical functions

Engineering Contradiction:

Improvedata integrityVSAvoidparity calculation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces the software-based parity calculation mechanism (which runs on the system processor) with hardware-based logic circuits implemented in the storage array controller. This substitution enables parallel computation and eliminates the sequential processing delays inherent in software execution, significantly reducing the time required for parity calculations while maintaining data integrity.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent performs parity calculations in advance during data write operations, so that parity information is ready before it is needed for potential recovery operations. This preliminary computation approach, enabled by dedicated hardware logic, eliminates delays that would occur if parity had to be calculated on-demand from the system processor.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12386703B2System and methods for parity calculation in storage arrays

Publication Date: 2025.08.12 MICROCHIP TECHNOLOGY INC

AI summary

A system may include a storage array comprised of one or more array member drives. The storage array may be partitioned into stripes of data across the one or more array member drives. In operation, a DMA controller may move source data from a processor memory and may write the data to an accelerator memory. The accelerator may perform a parity calculation and a DMA controller may write the parity result and the source data to at least one of the array member drives. The parity information may be used to reconstruct data in the one or more array member drives in the case of damage or loss of data.