DMA Controller Pattern Generation for Bus Traffic Reduction
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Solution Overview
Problem
DMA transfer in systems with high parallel processing architectures faces inefficiencies due to redundant data transfer of predetermined patterns like zero or unit matrices, leading to decreased memory use efficiency and complex system configurations.
Innovation Solution
A DMA transfer apparatus and method that includes a pattern generation section to create predetermined pattern data, a queuing section to synchronize data transfer, and a determination section to switch between transfer data and pattern data based on size, reducing bus traffic and simplifying system configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If predetermined pattern data (zero matrix or unit matrix) is stored in the external memory and transferred via DMA, then the data can be used for calculation, but the memory use efficiency decreases and redundant transfer occurs
Solution Approach 1:
The system pre-loads ordinary data into the external memory without anticipating future needs for pattern data. When pattern data is required, it is generated on-demand by the pattern generation section rather than being pre-stored, thus avoiding redundant memory occupancy and transfer while ensuring availability when needed.
Solution Approach 2:
The pattern generation section within the DMA controller automatically generates predetermined pattern data (zero matrices, unit matrices) when detected as needed, eliminating the dependency on pre-stored pattern data in external memory. This self-service capability ensures data availability without occupying memory resources unnecessarily.
2Productivity
If a function for generating predetermined pattern data is added in the calculation core, then memory use efficiency increases, but the system configuration becomes complex and processing flow must change
Solution Approach 1:
The pattern generation section acts as an intermediary component within the DMA controller that generates predetermined pattern data on-demand. This intermediary approach avoids the complexity of modifying the calculation core while still providing pattern generation capability, maintaining a clean separation between data transfer functions and calculation functions.
Solution Approach 2:
The DMA controller is enhanced with multi-functionality by incorporating the pattern generation section, allowing it to both transfer ordinary data and generate pattern data as needed. This universal capability eliminates the need for separate pattern generation hardware in the calculation core, reducing overall system complexity while improving memory efficiency.
3Reliability
If predetermined pattern data is transferred via DMA from external memory, then data is available for calculation, but bus traffic increases redundantly
Solution Approach 1:
The pattern generation section generates predetermined pattern data on-demand within the DMA controller itself, eliminating the need to transfer such data from external memory via the bus. This self-service generation capability ensures data availability for calculation while avoiding redundant bus traffic and associated energy consumption.
Solution Approach 2:
The system extracts the pattern generation function from the external memory and DMA transfer path, placing it directly within the DMA controller. This extraction eliminates the redundant bus transfer of pattern data while maintaining data availability, thereby reducing bus traffic and energy loss.
Data Source
AI summary
To provide a DMA transfer apparatus and a DMA transfer method capable of reducing traffic on a bus between an external shared memory and DMA controller with less additional hardware to effectively use a memory.A pattern generation section 11 is provided in a DMA controller 17 and generates data of a predetermined pattern, such as a zero matrix or unit matrix, in the DMA controller when data is transferred from an external shared memory 14 to an internal memory 15. Further, transfer data read out from the external shared memory is temporarily held in a queuing section 13 for queuing. At this time, switching between the transfer data from the queuing section and predetermined pattern data is made based on the number of the transfer data.