DMA Circuit Pattern Generation Unit for High-Speed I/O Verification
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Solution Overview
Problem
Current DMA circuits face challenges in performing effective load testing and verification, especially when dealing with high-speed I/O operations, as they struggle to generate a suitable data pattern for verification, leading to insufficient quality assurance and potential deterioration in storage server performance.
Innovation Solution
A DMA circuit is designed with a data pattern generation unit that creates a predetermined dummy data pattern for verification, allowing for efficient load testing of high-speed I/O operations by inserting a specific data pattern into padding data, enabling thorough performance verification without modifying the transfer data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DMA circuit performs data transfer using conventional methods, then data transfer functionality is achieved, but verification effectiveness and load testing capability are insufficient
Solution Approach 1:
The DMA circuit generates a predetermined data pattern in advance before actual data transfer operations. This preliminary action enables verification and load testing to be performed effectively without delaying the main data transfer functionality, thus improving reliability while maintaining productivity.
Solution Approach 2:
The DMA circuit incorporates a data pattern generation unit that enables it to verify its own performance and conduct load testing independently. This self-service capability allows the circuit to ensure its own reliability and performance without requiring external verification systems, thereby reducing the development cycle.
2Productivity
If a DMA circuit uses existing data transfer mechanisms, then basic data transfer is achieved, but load testing of high-speed I/O operations cannot be performed
Solution Approach 1:
The DMA circuit is designed with multi-functionality, incorporating both data transfer operations and data pattern generation for verification and load testing. This universal design allows the same circuit to perform both basic data transfer and advanced verification functions, improving load testing capability without proportionally increasing device complexity.
Solution Approach 2:
The data pattern generation unit acts as an intermediary component that enables load testing of high-speed I/O operations. It generates specific data patterns that can be used to stress-test the I/O interface without requiring fundamental changes to the overall circuit structure, thus improving testing capability while maintaining reasonable complexity.
3Reliability
If verification is performed thoroughly in storage server development, then quality assurance is improved, but verification time increases
Solution Approach 1:
The DMA circuit performs verification using predetermined data patterns generated in advance. This preliminary action allows verification to be conducted efficiently during development without requiring time-consuming thorough testing, thus improving quality assurance while minimizing verification time loss.
Solution Approach 2:
The system changes data transfer parameters by using specifically generated data patterns with different characteristics for verification purposes. This allows targeted verification of specific performance aspects without requiring complete re-testing, thereby improving quality assurance while reducing the time required compared to conventional verification methods.
Data Source
AI summary
In a send engine of a protocol/DMA control circuit, a descriptor control circuit obtains a descriptor, and notifies the information of the descriptor to each circuit. A dummy/padding generation circuit generates a data pattern according to the instruction of the descriptor. A write control circuit performs data transfer using the generated data pattern as a dummy transfer data according to the instruction of the descriptor. The write control circuit also inserts the generated data pattern into the transfer data as a padding data according to the instruction of the descriptor, and performs data transfer.