DMA Transaction Pipelining via Staging Buffer
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Solution Overview
Problem
Non-sequential data access operations in computer storage systems result in increased latency due to the need for multiple separate Direct Memory Access (DMA) transactions, which are inefficient and unacceptable in latency-sensitive applications.
Innovation Solution
A system and method for dynamic pipelining of DMA transactions using a staging buffer and an accelerator that transfers data blocks from a storage module to a staging buffer in a sequential order, allowing for early read responses to be sent to the host computer before all data is fetched, and delaying responses until data is available, thereby reducing the need for multiple polling schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple separate DMA transactions are used to access non-sequential source memory addresses, then data can be copied from non-sequential source areas to sequential destination area, but the latency of data access operations increases
Solution Approach 1:
The system performs preliminary actions by pre-fetching data blocks from non-sequential source addresses and storing them in a staging buffer before the host actually needs them. The accelerator receives a read list of future data block addresses and proactively transfers these blocks to the staging buffer in advance, so that when the host requests the data, it is already available or nearly available, thereby reducing access latency without requiring multiple separate DMA transactions to complete sequentially.
2Reliability
If all DMA transactions must be completed before data can be used by the requesting process, then data integrity is ensured, but the workflow is unacceptable in latency-sensitive applications
Solution Approach 1:
The accelerator performs preliminary data transfer actions by proactively fetching data blocks from storage and storing them in the staging buffer before the host process actually needs them. The host receives an acknowledgment that data will be available and can proceed with other operations while the data is being prepared, ensuring data integrity through the staged transfer mechanism while improving productivity by eliminating idle waiting time.
Solution Approach 2:
The staging buffer acts as an intermediary between the storage device and the host process. It receives data blocks from the storage device via DMA transactions and makes them available to the host process in a controlled manner. This intermediary mechanism ensures data integrity by completing transfers before making data available, while simultaneously improving productivity by allowing the host to access data as soon as it arrives in the staging buffer without waiting for all transfers to complete.
3Productivity
If the requesting process is divided into multiple sub-processes for pipelining, then DMA transactions can be pipelined with the requesting process, but a multiple polling scheme is required which increases system complexity
Solution Approach 1:
The invention extracts the polling complexity from the host process by implementing the data availability management entirely within the accelerator device. The accelerator independently monitors the completion of DMA transactions, manages the staging buffer, and determines when data is ready for the host. This extraction eliminates the need for the host to implement multiple polling schemes or divide itself into sub-processes, thereby maintaining high productivity through pipelining while significantly reducing system complexity.
Data Source
AI summary
A method and a system for pipelining read transactions of a host computer from a storage module, including: transferring from a host computer to an accelerator a read list, including at least one pointer to a data block stored on the storage module, and a respective data block size; sending an acknowledgement to the host; fetching at least one data block by the accelerator from the storage module, and writing it to a staging buffer in a sequential order; sending at least one read request from the host computer to the accelerator, relating to at least one requested data block. If the data block is available on the staging buffer, then sending the corresponding data to the host from the staging buffer. Otherwise the read response is delayed until the requested data is fetched from the storage module.