DMA-Based Power Capping Signal for Fast Server Power Spikes

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Solution Overview

Problem

Existing server power capping methods, such as firmware-based sampling and pulse-width modulation, fail to accurately manage power consumption spikes and are limited by firmware execution speed, reducing measurement accuracy.

Innovation Solution

The use of direct memory access (DMA) to generate hardware triggers for an analog-to-digital converter (ADC) engine, which converts analog voltage signals from servers to digital outputs and provides them to a programmable logic device for determining a power capping signal, increasing measurement frequency and accuracy through hardware-based controls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If firmware-based sampling is used to monitor power consumption, then the system can implement power capping control, but the measurement accuracy is reduced due to limited firmware execution speed and inability to capture power spikes between sampling times

Engineering Contradiction:

Improvepower measurement accuracyVSAvoidsampling frequency

Core Design Contradiction:

Measurement precisionVSSpeed

Solution Approach 1:

The patent replaces firmware-based sampling with a hardware-based measurement system using an analog-to-digital converter (ADC) engine that continuously monitors power consumption at the hardware level. This substitution enables much higher sampling frequencies and accurate capture of power spikes without being limited by firmware execution speed, directly resolving the contradiction between measurement accuracy and sampling frequency.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If firmware-based pulse-width modulation is used for power capping, then power control can be implemented, but the response time is limited by firmware execution speed

Engineering Contradiction:

Improvepower control reliabilityVSAvoidresponse time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces firmware-based PWM control with a hardware-based control mechanism where the ADC engine and direct memory access (DMA) operate at hardware speeds. This enables real-time power capping responses without the delays inherent in firmware execution, simultaneously improving control reliability and reducing response time.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system uses a hardware timer to generate periodic triggers that preemptively initiate power measurement and control actions. By preparing and executing control decisions at the hardware level before power spikes occur, the system achieves faster response times and more reliable power capping control.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If firmware-based power monitoring is used, then power consumption can be tracked, but the measurement frequency is limited reducing the ability to detect and respond to power consumption spikes

Engineering Contradiction:

Improvemeasurement frequencyVSAvoidpower spike detection accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent substitutes firmware-based periodic sampling with a hardware-based continuous monitoring system using the ADC engine triggered by hardware timers. This enables high-frequency measurements that accurately capture power consumption spikes, simultaneously improving both measurement frequency and detection accuracy.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the accuracy of power measurement and regulation by allowing more frequent monitoring and control of power consumption, effectively addressing the limitations of existing methods.

Implementation Method 1

an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine 104 may convert the analog voltage signal to a digital output.

Methodology Applied

Scientific EffectAnalog-to-digital conversion:

Data Source

PatentUS10725520B2Determining a power capping signal using direct memory access

Publication Date: 2020.07.28 HEWLETT PACKARD ENTERPRISE DEV LP

AI summary

Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.